The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 1994

Filed:

Aug. 07, 1992
Applicant:
Inventors:

Joseph Murray, Scottsdale, AZ (US);

Ned D Garinger, Tempe, AZ (US);

Peter H Sorrells, Chandler, AZ (US);

Assignee:

VLSI Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
327278 ; 327237 ;
Abstract

An output pad for an integrated circuit includes circuitry to align the output with an on-chip clock signal, and to compensate the output such that it remains coincident with the on-chip clock signal even when changes occur in power supply voltage, manufacturing process and temperature. This output pad has a closed-loop feedback circuit which controls the delay of the output signal through a variable delay element. The loop adjust the delay until the clock edge of the on-chip clock signal is coincident with the output signal within a defined tolerance. The output pad self-compensates with every clock cycle, which is many times faster than any induced variation.


Find Patent Forward Citations

Murray, Joseph. (1994). Self-compensating output pad for an integrated circuit and method (U.S. Patent No. 5365130). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5365130

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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