The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 2006
Filed:
Jul. 29, 2002
Ned D. Garinger, Tempe, AZ (US);
Martin L. Dorr, Chandler, AZ (US);
Mark W. Naumann, Tempe, AZ (US);
Gary A. Walker, Phoenix, AZ (US);
Ned D. Garinger, Tempe, AZ (US);
Martin L. Dorr, Chandler, AZ (US);
Mark W. Naumann, Tempe, AZ (US);
Gary A. Walker, Phoenix, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A network with memory device address decoding that enables communication among integrated processing elements, including a network, a processing element and a bus gasket. The network transfers packets between multiple ports, where each port conforms to a consistent port interface protocol. The processing element includes a bus and a memory device programmed with the address of each port, so that a transaction on the bus indicating another port is decoded by the memory device. The bus gasket includes a bus interface that generates packets and a port interface that sends and receives the packets according to the consistent port interface protocol and that uses the decoded address as a destination port address. The memory device may be implemented in any desired manner, such as a memory management unit (MMU) or a direct memory access (DMA) device.