logo

For the Inventor, By the Inventor

Kanagawa, Japan

Mutsunori Igarashi

This inventor holds 22 USPTO granted patents, primarily in Semiconductor Design. Top assignee: Kabushiki Kaisha Toshiba. Active years: 1993-2009.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Mutsunori Igarashi. Retrieved from https://idiyas.com/inventor/mutsunori-igarashi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 22

% Patents Active = 45.5

Average Co-Inventor Count = 2.7

ph-index = 12

Forward Citations = 1,312(Granted Patents)


Location History:

  • Kanagawa, JP (1995 - 1998)
  • Kanagawa-ken, JP (1999 - 2006)
  • Tokyo, JP (2002 - 2007)
  • Yokohama, JP (1993 - 2009)

Company Filing History:

goldMedal22 out of 53,262 
 
Kabushiki Kaisha Toshiba
 patents

Years Active: 1993-2009

Loading Chart...
Areas of Expertise:
Semiconductor Integrated Circuit
Noise Suppression Circuit
Automated Wiring Layout
Layout Design Method
ASIC
Pattern Correction
Low Power Consumption
Cell Arranging Method
Navigation Apparatus
Communication Circuit
Reticle Set
Design Program
22 patents (USPTO):Explore Patents
1. 7539952 - Computer implemented design system, a computer implemented design method, a reticle set, and an integrated circuit (2009-05-26),
2. 7230554 - Noise suppression circuit, ASIC, navigation apparatus, communication circuit, and communication apparatus having the same (2007-06-12),
3. 7127694 - Computer implemented design system, a computer implemented design method, a reticle set, and an integrated circuit (2006-10-24),
4. 7124389 - Automated wiring pattern layout method (2006-10-17),
5. 7064691 - Noise suppression circuit, ASIC, navigation apparatus, communication circuit, and communication apparatus having the same (2006-06-20),
6. 7013444 - Layout design system, layout design method and layout design program of semiconductor integrated circuit, and method of manufacturing the same (2006-03-14),
7. 6904572 - Method, apparatus and program for designing a semiconductor integrated circuit by adjusting loading of paths (2005-06-07),
8. 6813756 - Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program (2004-11-02),
9. 6792593 - Pattern correction method, apparatus, and program (2004-09-14),
10. 6779167 - Automated wiring pattern layout method (2004-08-17),
11. 6763508 - Layout design system, layout design method and layout design program of semiconductor integrated circuit, and method of manufacturing the same (2004-07-13),
12. 6683336 - SEMICONDUCTOR INTEGRATED CIRCUIT, SUPPLY METHOD FOR SUPPLYING MULTIPLE SUPPLY VOLTAGES IN SEMICONDUCTOR INTEGRATED CIRCUIT, AND RECORD MEDIUM FOR STORING PROGRAM OF SUPPLY METHOD FOR SUPPLYING MULTIPLE SUPPLY VOLTAGES IN SEMICONDUCTOR INTEGRATED CIRCUIT (2004-01-27),
13. 6645842 - Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method (2003-11-11),
14. 6546540 - Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program (2003-04-08),
15. 6459331 - Noise suppression circuit, ASIC, navigation apparatus communication circuit, and communication apparatus having the same (2002-10-01),

Title: Mutsunori Igarashi: Innovator in Circuit Design and Noise Suppression Technologies

Introduction

Mutsunori Igarashi, based in Kanagawa-ken, Japan, is a prominent inventor known for his contributions to the fields of circuit design and noise suppression technologies. With an impressive portfolio of 22 patents, he has made significant strides in the development of innovative systems that are pivotal in modern electronics.

Latest Patents

Igarashi's latest patents focus on advanced designs within the realm of computer-implemented systems and noise suppression circuits. Notable inventions include:

1. **Computer Implemented Design System and Method**: This invention features a reticle set that includes three distinct reticles:

- The first reticle has a unique wiring pattern with a termination pattern.

- The second reticle is characterized by multiple via patterns.

- The third reticle contains another wiring pattern alongside a connected line pattern.

2. **Noise Suppression Circuit and Communication Apparatus**: This innovative circuit design includes:

- An internal circuit with high and low level terminals, linking to a low level power supply (GND).

- A configuration with two transistors to manage conductivity based on circuit activity.

- A communication circuit that minimizes data bus additions while encoding data to harmonize the number of '0's and '1's transferring through the data buses, effectively reducing common phase power supply noise.

- Additionally, a bypass capacitor formed within an ASIC, aimed at mitigating EMI noise, adds further advancement to his work.

Career Highlights

Igarashi's career is marked by his tenure at Kabushiki Kaisha Toshiba, where he has led significant projects that challenge conventional design approaches. His inventive spirit and technical prowess have not only fostered innovation but have also substantially impacted the development of reliable electronic systems.

Collaborations

Throughout his career, Igarashi has had the opportunity to collaborate with esteemed colleagues, including Masaaki Yamada and Masami Murakata. Their collective expertise has been instrumental in driving projects that push the boundaries of current technology.

Conclusion

Mutsunori Igarashi stands as a beacon of innovation in the electronics industry. His extensive patent portfolio and pioneering designs continue to shape the future of circuit design and noise management, ensuring that modern technological systems are both efficient and effective. As he forges ahead, Igarashi's contributions will undoubtedly leave a lasting legacy in the field.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…