The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7013444 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 14, 2006

Filed:

Apr. 14, 2004
Applicants:

Mutsunori Igarashi, Yokohama, JP;

Takashi Mitsuhashi, Fujisawa, JP;

Inventors:

Mutsunori Igarashi, Yokohama, JP;

Takashi Mitsuhashi, Fujisawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A layout design system of a semiconductor integrated circuit, comprising: a library information storage unit configured to register a basic via shape list; a technology database storage unit configured to register a list expressing an optimum wire terminating process for each via shape of said basic via shape list registered in said library information storage unit; and a central processing control unit configured to refer to the lists respectively registered in said library information storage unit and said technology database storage unit, select an optimum line processing, and execute a line design.


Find Patent Forward Citations

Igarashi, Mutsunori. (2006). Layout design system, layout design method and layout design program of semiconductor integrated circuit, and method of manufacturing the same (U.S. Patent No. 7013444). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7013444

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