Mitsunori Tsujino

This inventor holds 11 USPTO granted patents. Top assignees: Mitsubishi Denki Kabushiki Kaisha, Renesas Technology Corp.. Active years: 1998-2005.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Mitsunori Tsujino. Retrieved from https://idiyas.com/inventor/mitsunori-tsujino

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 11

% Patents Active = 63.6

Average Co-Inventor Count = 1.5

ph-index = 7

Forward Citations = 102(Granted Patents)

Location History:

Tokyo, JP (1998 - 2003)
Hyogo, JP (1999 - 2005)

Company Filing History:

8 out of 21,351

Mitsubishi Denki Kabushiki Kaisha

patents

3 out of 3,781

Renesas Technology Corp.

patents

Years Active: 1998-2005

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11 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 6949986 - Semiconductor device unlikely to make incorrect determination of fuse blow (2005-09-27),

2. 6744691 - Semiconductor memory module (2004-06-01),

3. 6700414 - Phase comparator accurately comparing phases of two clock signals and clock generation circuit employing the same (2004-03-02),

4. 6665225 - Semiconductor integrated circuit with reduction of self refresh current (2003-12-16),

5. 6653877 - Semiconductor device capable of internally adjusting delayed amount of a clock signal (2003-11-25),

6. 6519194 - Semiconductor memory device with a rapid packet data input, capable of operation check with low speed tester (2003-02-11),

7. 6366517 - Semiconductor integrated circuit capable of readily adjusting circuit characteristic (2002-04-02),

8. 6301190 - Semiconductor memory device with a rapid packet data input, capable of operation check with low speed tester (2001-10-09),

9. 6201380 - Constant current/constant voltage generation circuit with reduced noise upon switching of operation mode (2001-03-13),

10. 5874772 - Semiconductor device (1999-02-23),

11. 5841164 - Test structure for dielectric film evaluation (1998-11-24),

Title: Mitsunori Tsujino: Innovator in Semiconductor Technology

Introduction

Mitsunori Tsujino is a prominent inventor based in Hyogo, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 11 patents. His work focuses on improving the reliability and functionality of semiconductor devices.

Latest Patents

One of Tsujino's latest patents is a semiconductor device designed to avoid incorrect determination of fuse blow states. By switching a mode signal, the capability of a drive circuit in a latch circuit can be enhanced compared to normal mode. This innovation ensures that even if a small leakage occurs in a blown portion of a fuse element, the blow can be accurately identified. This improvement in drivability of the latch circuit helps prevent incorrect determinations of fuse blow states. Another notable patent is for a semiconductor memory module that incorporates repair chips. These chips allow for the proper functioning of BANKs even when some have become defective. By effectively utilizing the functions of non-defective banks, this design enhances the overall reliability of semiconductor memory modules.

Career Highlights

Throughout his career, Mitsunori Tsujino has worked with notable companies such as Mitsubishi Electric Corporation and Renesas Technology Corporation. His experience in these organizations has contributed to his expertise in semiconductor technology and innovation.

Collaborations

Tsujino has collaborated with several professionals in his field, including Kazutoshi Hirayama and Kyoji Yamasaki. These collaborations have likely fostered advancements in semiconductor technology and innovation.

Conclusion

Mitsunori Tsujino's contributions to semiconductor technology through his patents and collaborations highlight his role as a key innovator in the industry. His work continues to influence the development of reliable and efficient semiconductor devices.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]