The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 25, 2003
Filed:
Dec. 22, 2000
Applicant:
Inventor:
Mitsunori Tsujino, Hyogo, JP;
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03H 1/126 ;
U.S. Cl.
CPC ...
H03H 1/126 ;
Abstract
A plurality of internal circuits each include a respective clock adjusting circuit that adjusts the phase of a clock signal given by a clock buffer. Even if a difference in delayed amount of the clock signal is generated by drawing clock interconnections, a different adjustment can be made for each internal circuit, whereby the operation of synchronized circuits respectively included in the plurality of internal circuits can be improved.
Tsujino, Mitsunori. (2003). Semiconductor device capable of internally adjusting delayed amount of a clock signal (U.S. Patent No. 6653877). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6653877
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile