This inventor holds 2 USPTO granted patents. Top assignee: Synopsys, Inc.. Active years: 2022-2026.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2022-2026
Title: Mihir Sherlekar: Advancing Analog Circuit Defect Analysis
Introduction
Mihir Sherlekar is an inventor based in Mountain View, California, whose patented work addresses defect detection and simulation in analog circuit design. He is associated with Synopsys, Inc., and holds 2 patents.
Latest Patents
“Maximizing Detectable Defect Coverage of Analog Circuits in Integrated Circuit Design” describes a method for identifying detectable defects in an analog circuit. It compares defects found through detectability analysis with those identified through user-defined analysis, then groups defects not covered by the user analysis into clusters.
“Guiding Sample Size Choice in Analog Defect or Fault Simulation” presents a method for evaluating sampling sizes in circuit simulation. It organizes coverage scenarios into bins, estimates sampling error, and generates confidence scores to help assess the reliability of coverage results.
Career Highlights
Sherlekar’s patented inventions focus on improving how engineers analyze defects and evaluate simulation coverage in analog circuits. These methods support more systematic defect assessment and informed choices about simulation sampling.
Collaborations
Sherlekar’s listed coworkers include Mayukh Bhattacharya and Huiping Huang. His work is associated with Synopsys, Inc.
Conclusion
Mihir Sherlekar’s patents contribute methods for identifying analog circuit defects and evaluating the confidence of simulation coverage.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile