Tokyo, Japan

Masakazu Amanai

This inventor holds 10 USPTO granted patents. Top assignee: Nec Corporation. Active years: 1994-2001.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Masakazu Amanai. Retrieved from https://idiyas.com/inventor/masakazu-amanai

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 1.6

ph-index = 6

Forward Citations = 78(Granted Patents)


Company Filing History:


Years Active: 1994-2001

Loading Chart...
10 patents (USPTO):Explore Patents

Title: Innovations by Masakazu Amanai

Introduction

Masakazu Amanai, a prominent inventor based in Tokyo, Japan, has made significant contributions to the field of semiconductor technology. With a total of 10 patents to his name, his work has been instrumental in advancing modern electronic devices. Currently affiliated with NEC Corporation, Amanai's innovations reflect his expertise and dedication to enhancing semiconductor functionalities.

Latest Patents

Among his latest creations, Amanai has developed two noteworthy patents that showcase his ingenuity. The first is a **Level Shifting Circuit**, which describes a semiconductor device comprising a level shifting circuit that can be achieved without using an extra charge pump and utilizing low-voltage transistors. This circuit effectively controls the on/off state of a transfer gate, specifically an n-channel transistor N. The design incorporates a NAND gate that receives the voltage mode selection signal HVON and input signal IN. Additionally, the configuration includes p-channel and n-channel transistors series-connected between the NAND gate output and the -9V charge pump output (Vncp).

His second recent patent is for a **Semiconductor Memory with PN Junction Potential Reduction in Writing**. This invention consists of a semiconductor memory device featuring multiple memory cells arranged in a matrix form, with a row sub-decoder and a row main decoder. The row main decoder decodes a row address signal and delivers a control signal to the row sub-decoder. Importantly, the row main decoder is constructed with at least one transistor that possesses a PN junction breakdown voltage, and the reducing means effectively lowers this breakdown voltage during the writing mode.

Career Highlights

Throughout his career at NEC Corporation, Amanai has focused on innovative solutions within semiconductor technology. His relentless pursuit of advancements has not only garnered him multiple patents but has also positioned him as a key contributor in the industry. His work exemplifies a strong commitment to enhancing the performance and efficiency of semiconductor devices.

Collaborations

Amanai has collaborated with talented colleagues such as Masaki Kaneko and Hiroyuki Kobatake. Together, they have fostered an environment of creativity and innovation, pushing the boundaries of semiconductor technology through their shared expertise and collaborative efforts.

Conclusion

Masakazu Amanai stands out as a visionary inventor whose contributions to semiconductor technology continue to shape the industry. With a solid portfolio of patents, his innovations reflect a profound understanding of electronic systems and their intricacies. As he moves forward in his career, it is anticipated that he will further enhance the landscape of technology, benefiting countless applications and consumers worldwide.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…