Semiconductor memory device having a bias control circuit for erase

Abstract

The semiconductor memory device according to this invention includes a plurality of word lines each connected to an electrically writable and erasable memory cell, a first terminal which goes to the active level when the word line is selected, a second terminal to which is applied a read voltage during the period of read operation and a write voltage which is higher than the read voltage during the period of write operation, a transfer gate provided between the second terminal and a node and has its control terminal connected to the first terminal, bias supply means which connects the node to a power terminal when the first terminal is at the inactive level and brings the node to the cutoff state when the first terminal is at the active level, a negative voltage generation circuit which supplies a negative voltage to the word line during the period of data erase operation, a transistor provided between the node and one end of the word line, and a bias control circuit which supplies a bias voltage which brings the transistor to the off-state during the period of data erase operation and brings the transistor to the on-state during the periods of write and read operations, wherein the bias control circuit is so set as to give the bias voltage generated when the first terminal is at the active level lower compared with the bias voltage generated when the first terminal is at the nonactive level.