The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2000
Filed:
Mar. 29, 1999
Applicant:
Inventor:
Masakazu Amanai, Tokyo, JP;
Assignee:
NEC Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36518523 ; 36518504 ;
Abstract
A semiconductor memory device includes a plurality of memory cells, a row sub-decoder, a row main decoder and reducing means. The memory cells are arranged in a matrix form. The row sub-decoder selects each row of the memory cells. The row main decoder decodes a row address signal and supplies a control signal into the row sub-decoder. The row main decoder is structured by at least one transistor having a PN junction breakdown voltage. The reducing means reduces the PN junction breakdown voltage during a writing mode.
Amanai, Masakazu. (2000). Semiconductor memory with pn junction potential reduction in a writing (U.S. Patent No. 6128230). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6128230
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile