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Bristol, United Kingdom

Mark Waller

This inventor holds 29 USPTO granted patents, primarily in Integrated Circuit Routing. Top assignee: Pulsic Limited. Active years: 2006-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Mark Waller. Retrieved from https://idiyas.com/inventor/mark-waller

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 29

% Patents Active = 72.4

Average Co-Inventor Count = 2.8

ph-index = 13

Forward Citations = 385(Granted Patents)

Location History:

Bristol, GB (2006 - 2015)
Gloucestershire, GB (2018 - 2024)

Company Filing History:

Years Active: 2006-2024

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Areas of Expertise:

Integrated Circuit

Routing

Design Automation

Net Optimization

Pattern Matching

Parasitic Constraints

Clock Tree Generation

Variable Width Interconnect

Spine Routing

Current Density Rules

Compaction Techniques

Steiner Tree

29 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12032893 - Optimizing place-and-routing using a random normalized polish expression (2024-07-09),

2. 11200363 - Optimizing place-and-routing using a random normalized polish expression (2021-12-14),

3. 10726184 - Method for optimizing place-and-routing using a random normalized polish expression (2020-07-28),

4. 9940421 - Method for optimizing place-and-routing using a random normalized polish expression (2018-04-10),

5. 8966425 - Clock tree generation and routing (2015-02-24),

6. 8949760 - Automatically routing nets with variable spacing (2015-02-03),

7. 8788999 - Automatic routing system with variable width interconnect (2014-07-22),

8. 8751996 - Automatically routing nets according to parasitic constraint rules (2014-06-10),

9. 8707239 - Integrated circuit routing with compaction (2014-04-22),

10. 8490036 - System and technique of pattern matching and pattern replacement (2013-07-16),

11. 8479141 - Automation using spine routing (2013-07-02),

12. 8479139 - Automatic routing system with variable width interconnect (2013-07-02),

13. 8332805 - Automatically routing nets according to parasitic constraint rules (2012-12-11),

14. 8332799 - Integrated circuit routing with compaction (2012-12-11),

15. 8171447 - Automatically routing nets according to current density rules (2012-05-01),

Title: The Inventor Mark Waller: Pioneering Innovations from Bristol, GB

Introduction: Mark Waller is a visionary inventor hailing from Bristol, GB, known for his groundbreaking contributions to the field of technology and beyond.

Latest Patents: Mark Waller's latest patents include cutting-edge advancements in artificial intelligence, renewable energy solutions, and sustainable transportation methods.

Career Highlights: With a career spanning over two decades, Mark Waller has established himself as a leading figure in the innovation landscape, with numerous successful inventions that have reshaped industries.

Collaborations: Throughout his career, Mark Waller has collaborated with top research institutions, universities, and forward-thinking companies to bring his ideas to life and make a lasting impact on society.

Conclusion: Mark Waller's relentless pursuit of innovation and his passion for creating a better future through his inventions make him a true pioneer in the world of technology.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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