The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2020
Filed:
Apr. 10, 2018
Applicant:
Pulsic Limited, Bristol, GB;
Inventors:
Mark Waller, Gloucestershire, GB;
Paul Clewes, Northumberland, GB;
Liang Gao, Gateshead, GB;
Jonathan Longrigg, Newcastle upon Tyne, GB;
Assignee:
Pulsic Limited, Bristol, GB;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 30/392 (2020.01); G06F 30/39 (2020.01); G06F 30/394 (2020.01); G09G 3/20 (2006.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/39 (2020.01); G06F 30/394 (2020.01); G09G 3/2088 (2013.01);
Abstract
Simultaneous automatic placement and routing speeds up implementation an integrated circuit layout and improves the resulting layout such that the layout is more compact, has reduced parasitics, and has improved circuit performance characteristics (e.g., power, frequency, propagation delay, gain, and stability). A technique generates solutions based on random normalized polish expression, and includes cost considerations based on routing of interconnect.