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For the Inventor, By the Inventor

Cary, NC, United States of America

Manish Garg

This inventor holds 24 USPTO granted patents and 2 published patent applications and 15 EPO patents, primarily in Memory Systems. Top assignee: Qualcomm Incorporated. Active years: 2010-2023.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Manish Garg. Retrieved from https://idiyas.com/inventor/manish-garg

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 24 

% Patents Active = 66.7

 

Average Co-Inventor Count = 2.5

ph-index = 6

Forward Citations = 89(Granted Patents)


Location History:

  • Morrisville, NC (US) (2010 - 2016)
  • Cary, NC (US) (2015 - 2023)

Company Filing History:

goldMedal24 out of 44,831 
 
Qualcomm Incorporated
 patents

Years Active: 2010-2023

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Areas of Expertise:
Load Instructions
Sense Amplifier
Memory Array Failures
Voltage Level Shifter
Power Rail Control
N-bit Compare Logic
Read-Write Operations
Collision Detection
Adaptive Scheduling
SRAM Cell
Low Leakage
Storage Element
24 patents (USPTO):Explore Patents
1. 11593117 - Combining load or store instructions (2023-02-28),
2. 10559352 - Bitline-driven sense amplifier clocking scheme (2020-02-11),
3. 10541044 - Providing efficient handling of memory array failures in processor-based systems (2020-01-21),
4. 10171080 - Voltage level shifter (VLS) circuits employing a pre-conditioning circuit for pre-conditioning an input signal to be voltage level shifted in response to a pre-charge phase (2019-01-01),
5. 10050448 - Providing current cross-conduction protection in a power rail control system (2018-08-14),
6. 9960759 - N-bit compare logic with single ended inputs (2018-05-01),
7. 9911472 - Write bitline driver for a dual voltage domain (2018-03-06),
8. 9870818 - Separate read and write address decoding in a memory system to support simultaneous memory read and write operations (2018-01-16),
9. 9768779 - Voltage level shifters employing preconditioning circuits, and related systems and methods (2017-09-19),
10. 9666269 - Collision detection systems for detecting read-write collisions in memory systems after word line activation, and related systems and methods (2017-05-30),
11. 9495503 - Method and apparatus to enable a selective push process during manufacturing to improve performance of a selected circuit of an integrated circuit (2016-11-15),
12. 9396794 - Matchline retention for mitigating search and write conflict (2016-07-19),
13. 9129706 - Dummy read to prevent crowbar current during read-write collisions in memory arrays with crosscoupled keepers (2015-09-08),
14. 9093125 - Low voltage write speed bitcell (2015-07-28),
15. 9043795 - Apparatus and methods for adaptive thread scheduling on asymmetric multiprocessor (2015-05-26),

Title: The Innovative Journey of Manish Garg

Introduction: Manish Garg, a talented inventor based in Cary, NC (US), has made significant contributions to the field of technology through his creative innovations and patented inventions.

Latest Patents: Manish Garg holds several patents in the areas of artificial intelligence, machine learning, and robotics, showcasing his expertise in cutting-edge technologies.

Career Highlights: With a background in computer science and engineering, Manish Garg has a successful career marked by groundbreaking inventions that have revolutionized the industry. His dedication to pushing the boundaries of innovation is evident in the impact of his work.

Collaborations: Throughout his career, Manish Garg has collaborated with leading tech companies and research institutions to further develop his inventions and bring them to market. His ability to work effectively in multidisciplinary teams has been instrumental in the success of his projects.

Conclusion: Manish Garg's passion for innovation and his commitment to excellence continue to drive his success as an inventor, making him a respected figure in the technology sector.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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