The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2015
Filed:
Jan. 22, 2013
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Joshua L. Puckett, Raleigh, NC (US);
Manish Garg, Morrisville, NC (US);
Harish Shankar, Raleigh, NC (US);
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 11/412 (2006.01); G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 7/00 (2013.01); G11C 11/412 (2013.01); G11C 11/419 (2013.01);
Abstract
In low power CPUs, the best way to reduce power is to reduce supply voltage. Most low voltage memory arrays use an 8T cell, which has read stability immunity, in order to operate at low voltages. An embodiment of the disclosure determines when a write wordline (WWL) rises. If the determination shows that the WWL has risen, at least one of the plurality of p-channel field effect transistors (pFETS) is disconnected from a voltage supply, and the at least one plurality of n-channel field effect transistors (nFET) passgate transistors are opened.