Qualcomm Incorporated

Manish Garg

Michael ThaiThanh Phan

Chiaming Chai

Harish Shankar

Rahul Krishnakumar Nadkarni

David Paul Hoff

Thomas Philip Speier

Michael W Morrow

Stephen Edward Liles

Rajesh Kumar

Joshua Lance Puckett

James Norris Dieffenderfer

Rodney Wayne Smith

Zhongze Wang

Jeffrey Todd Bridges

Brian Stempel

Yeshwant Nagaraj Kolla

Jeffrey Herbert Fischer

Yusuf Cagatay Tekmen

Kevin Neal Magill

Quan Van Nguyen

Fadi Adel Hamdan

Shaoping Ge

Neel Shashank Natekar

Clint Wayne Mumford

Pritha Ghoshal

Kshitiz Saxena

Michael Thai Thanh Phan

Ramasamy Adaikkalavan

Sang Hoon Lee

Viren Ramesh Patel

Paul Steinmetz

Harsh Thakker

Kevin Jaget

Michael Thaithanh Phan

Michael Phan

Quan Nguyen

Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.

Combining load or store instructions

A memory system includes a sense amplifier electrically coupled to a first bitline and a second bitline associated with a column of a memory array, a bl transistor electrically coupled to the first bitline, wherein the bl transistor is configured to receive as input a first electrical signal from the first bitline, and a blb transistor electrically coupled to the second bitline, wherein the blb transistor is configured to receive as input a second electrical signal from the second bitline, wherein an output of the bl transistor and an output of the blb transistor are electrically coupled together as a common output, and wherein the sense amplifier is configured to receive as an input the common output of the bl transistor and the blb transistor.

Bitline-driven sense amplifier clocking scheme

Providing efficient handling of memory array failures in processor-based systems is disclosed. In this regard, in one aspect, a memory controller of a processor-based device is configured to detect a defect within a memory element of a plurality of memory elements of a memory array. In response, a disable register of one or more disable registers is set to correspond to the memory element to indicate that the memory element is disabled. The memory controller receives a memory access request to a memory address corresponding to the memory element, and determines, based on one or more disable registers, whether the memory element is disabled. If so, the memory controller disallows the memory access request. Some aspects may provide that the memory controller, in response to detecting the defect, provides a failure indication to an executing process, and subsequently receives, from the executing process, a request to set the disable register.

Providing efficient handling of memory array failures in processor-based systems

Voltage level shifter (VLS) circuits employing a pre-conditioning circuit for pre-conditioning an input signal to be voltage level shifted in response to a pre-charge phase are disclosed. A VLS circuit is configured to voltage level shift an input signal in a lower voltage domain on an output node in a higher voltage domain. The VLS circuit includes a pre-charge circuit configured to pre-charge the output node in a pre-charge phase. The VLS circuit also includes a pull-up circuit and a pull-down circuit that are configured to pull-up and pull-down the pre-charge phase of the output node, respectively, in an evaluation phase based on a logic state of the input signal to generate the output signal. To mitigate or avoid contention between the pull-up and pull-down circuits in the evaluation phase, the input signal is pre-conditioned such that the pull-down circuit is deactivated in response to the pre-charge phase.

Voltage level shifter (VLS) circuits employing a pre-conditioning circuit for pre-conditioning an input signal to be voltage level shifted in response to a pre-charge phase

Power rail control systems that include power multiplexing circuits that include cross-current conduction protection are disclosed. Power multiplexing circuit includes supply selection circuits each coupled between a respective supply power rail and an output power rail coupled to a powered circuit. To maintain power to the powered circuit during switching coupling of the output power rail, but while also avoiding current cross-conduction path between supply power rails, diode drop control circuits are provided in supply selection circuits. In diode drop operation mode, the diode drop control circuit associated with a higher voltage supply power rail is configured to regulate voltage supplied by such supply power rail to the output power rail to power the powered circuit. A current cross-conduction path is not created, because diode drop control circuits associated with lower voltage supply power rails are reverse biased to prevent current from flowing through their associated supply selection circuits.

Providing current cross-conduction protection in a power rail control system

Disclosed systems and methods relate to comparison of a first number and a second number. A comparator receives first and second single-ended inputs (i.e., not represented in differential format), which may be n-bits wide, wherein the first input is an inverted version of the first number and the second input is a true version of the second number. A partial match circuit is implemented to generate a partial match output based only on the first single-ended input and the second single-ended input. A partial mismatch circuit is implemented to generate a partial mismatch output based only on the first single-ended input and the second single-ended input. A comparison output circuit is implemented to generate a comparison output of the first and second numbers based on the partial match output and the partial mismatch output.

N-bit compare logic with single ended inputs

Systems and methods are directed to managing signals in a dual voltage domain comprising a high voltage domain and a low voltage domain. A write bitline driver circuit receives complementary global write bitline signals as input signals from a global write bitline driver in the low voltage domain, and a write enable signal as an input signal in the high voltage domain. The write bitline driver circuit generates complementary local write bitline signals as output signals in the high voltage domain for activating bitlines of a memory bank in the high voltage domain. The complementary local write bitline signals are based on the complementary global write bitline signals, voltage level shifted from the low voltage domain to the high voltage domain and gated by the write enable signal.

Write bitline driver for a dual voltage domain

Memory systems that provide separate read and write address decoding to support simultaneous memory read and write operations are disclosed. Separating read and write address decoding can avoid circuit conflicts for a simultaneous memory read and write operation even if employing single port memory bit cells. The read and write addresses of respective read and write operations are separately decoded into read and write row and column selects driven to a memory array so that simultaneous read and write operations are not affected by each other. To avoid a circuit conflict for a simultaneous read and write operation, the memory system is configured to prioritize a write row select over a read row select to drive a row of memory bit cells in the memory array. In this manner, that write operation will always be successful regardless of whether the read and write row select are to the same row.

Separate read and write address decoding in a memory system to support simultaneous memory read and write operations

Voltage level shifters employing preconditioning circuits are disclosed. Related systems and methods are also disclosed. In one aspect, voltage level shifter is configured to generate a voltage level shifted non-complement output signal and complement output signal corresponding to non-complement input signal and complement input signal, respectively. First pull-up circuit is configured to generate complement output signal in response to non-complement input signal transitioning to logic low voltage. First pull-down circuit is configured to generate non-complement output signal in response to complement input signal transitioning to logic high voltage. First preconditioning circuit is configured to receive non-complement and complement output signals and generate and provide shifted voltage signal to complement output in response to non-complement output signal transitioning to logic low voltage. This allows the complement output signal to transition to the shifted voltage more quickly.

Voltage level shifters employing preconditioning circuits, and related systems and methods

Collision detection systems for detecting read-write collisions in memory systems after word line activation are disclosed. In one aspect, a collision detection system is provided. The collision detection system includes a collision detection circuit for each bit cell row of memory array. Each collision detection circuit is configured to receive a write and read word line signal corresponding to the bit cell row. The collision detection circuit is configured to detect a write and read word line signal pair being active for a write and read operation for the same bit cell row. The collision detection circuit is configured to generate a collision detection signal to notify clients associated with the memory system that a read-write collision occurred. Detecting the read-write collisions after read word line activation reduces or avoids overhead delays in the read path, as opposed to detecting read-write collisions prior to activation of the read word line.

Collision detection systems for detecting read-write collisions in memory systems after word line activation, and related systems and methods

Provided are methods and apparatus for enabling selective push processing during design and fabrication of an integrated circuit to improve performance of selected circuits of the integrated circuit. An exemplary method includes identifying a critical portion of an integrated circuit layout that defines a functional element having a critical operating frequency requirement and designing a subcircuit in the critical portion to enable performing a speed push process to increase performance of the subcircuit. The method can also include identifying at least one of a power supply node, a clock supply node, and an interface node at a boundary between the critical portion and a portion of the integrated circuit that is outside of the critical portion. The critical portion can be designed with a power domain that is independent of the portion of the integrated circuit that is outside of the critical portion.

Method and apparatus to enable a selective push process during manufacturing to improve performance of a selected circuit of an integrated circuit

Systems and methods relate to a matchline receiver of a content-addressable memory (CAM). A matchline of the CAM, which provides a hit/miss indication for a search operation of a data word is provided to the matchline receiver. The matchline receiver comprises a retention circuit to provide a hit/miss output, wherein the retention circuit retains, at the hit/miss output, the hit/miss indication provided by the matchline during a first clock phase of a clock, even if the hit/miss indication provided by the matchline is modified by a write operation or an invalidation operation during the first clock phase.

Matchline retention for mitigating search and write conflict

Systems and methods for detecting and suppressing crowbar currents in memory arrays. A dummy read is implemented to prevent crowbar currents in the case of simultaneous read-write collisions in a static random access memory (SRAM) array having cross-coupled bitline keepers. When a simultaneous read and write operation to a first entry of the memory array is detected, the read operation to the first entry is suppressed and a dummy read operation to a second entry of the memory array is performed. The write operation to the first entry is allowed to proceed undisturbed.

Dummy read to prevent crowbar current during read-write collisions in memory arrays with crosscoupled keepers

In low power CPUs, the best way to reduce power is to reduce supply voltage. Most low voltage memory arrays use an 8T cell, which has read stability immunity, in order to operate at low voltages. An embodiment of the disclosure determines when a write wordline (WWL) rises. If the determination shows that the WWL has risen, at least one of the plurality of p-channel field effect transistors (pFETS) is disconnected from a voltage supply, and the at least one plurality of n-channel field effect transistors (nFET) passgate transistors are opened.

Low voltage write speed bitcell

Techniques for adaptive thread scheduling on a plurality of cores for reducing system energy are described. In one embodiment, a thread scheduler receives leakage current information associated with the plurality of cores. The leakage current information is employed to schedule a thread on one of the plurality of cores to reduce system energy usage. On chip calibration of the sensors is also described.

Growing community of inventors

Cary, NC, United States of America

Manish Garg