The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 21, 2020
Filed:
Jul. 06, 2017
Qualcomm Incorporated, San Diego, CA (US);
Thomas Philip Speier, Wake Forest, NC (US);
Viren Ramesh Patel, Morrisville, NC (US);
Michael Phan, Cary, NC (US);
Manish Garg, Cary, NC (US);
Kevin Magill, Durham, NC (US);
Paul Steinmetz, Apex, NC (US);
Clint Mumford, Apex, NC (US);
Kshitiz Saxena, Cary, NC (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
Providing efficient handling of memory array failures in processor-based systems is disclosed. In this regard, in one aspect, a memory controller of a processor-based device is configured to detect a defect within a memory element of a plurality of memory elements of a memory array. In response, a disable register of one or more disable registers is set to correspond to the memory element to indicate that the memory element is disabled. The memory controller receives a memory access request to a memory address corresponding to the memory element, and determines, based on one or more disable registers, whether the memory element is disabled. If so, the memory controller disallows the memory access request. Some aspects may provide that the memory controller, in response to detecting the defect, provides a failure indication to an executing process, and subsequently receives, from the executing process, a request to set the disable register.