The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2020

Filed:

Sep. 18, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Harish Shankar, Cary, NC (US);

Manish Garg, Cary, NC (US);

Rahul Krishnakumar Nadkarni, Cary, NC (US);

Rajesh Kumar, San Diego, CA (US);

Michael Phan, Cary, NC (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/419 (2006.01); G11C 7/08 (2006.01); G11C 8/18 (2006.01); G11C 7/10 (2006.01); G11C 11/418 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 7/08 (2013.01); G11C 7/1042 (2013.01); G11C 8/18 (2013.01); G11C 11/418 (2013.01);
Abstract

A memory system includes a sense amplifier electrically coupled to a first bitline and a second bitline associated with a column of a memory array, a bl transistor electrically coupled to the first bitline, wherein the bl transistor is configured to receive as input a first electrical signal from the first bitline, and a blb transistor electrically coupled to the second bitline, wherein the blb transistor is configured to receive as input a second electrical signal from the second bitline, wherein an output of the bl transistor and an output of the blb transistor are electrically coupled together as a common output, and wherein the sense amplifier is configured to receive as an input the common output of the bl transistor and the blb transistor.


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