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For the Inventor, By the Inventor

Berkeley, CA, United States of America

Luciano Lavagno

This inventor holds 18 USPTO granted patents and 2 published patent applications. Top assignees: Cadence Design Systems, Inc., Esilicon Corporation, Xilinx, Inc.. Active years: 1997-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Luciano Lavagno. Retrieved from https://idiyas.com/inventor/luciano-lavagno

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 18 

% Patents Active = 66.7

Average Co-Inventor Count = 3.3

ph-index = 7

Forward Citations = 135(Granted Patents)


Location History:

  • San Jose, CA (US) (2012)
  • Turin, IT (2013 - 2021)
  • Berkeley, CA (US) (1997 - 2022)

Company Filing History:

goldMedal11 out of 2,619 
 
Cadence Design Systems, Inc.
 patents
silverMedal3 out of 30 
 
Esilicon Corporation
 patents
bronzeMedal2 out of 5,108 
 
Xilinx, Inc.
 patents
4. 1 out of 3 
 
Institute of Computer Science, Foundation for Research and Technology- Hellas
 patents
5. 1 out of 41 
 
Sisvel Technology S.r.l.
 patents

Years Active: 1997-2025

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18 patents (USPTO):Explore Patents
1. 12468581 - Inter-kernel dataflow analysis and deadlock detection (2025-11-11),
2. 11520570 - Application-specific hardware pipeline implemented in an integrated circuit (2022-12-06),
3. 11048008 - Capacitive sensor and method for sensing changes in a space (2021-06-29),
4. 8572539 - Variability-aware scheme for high-performance asynchronous circuit voltage regulation (2013-10-29),
5. 8446224 - Network of tightly coupled performance monitors for determining the maximum frequency of operation of a semiconductor IC (2013-05-21),
6. 8433875 - Asynchronous scheme for clock domain crossing (2013-04-30),
7. 8286108 - System and method for synthesis reuse (2012-10-09),
8. 7873948 - Method and system for split-compiling a hybrid language program (2011-01-18),
9. 7870516 - Asynchronous, multi-rail, asymmetric-phase, static digital logic with completion detection and method for designing the same (2011-01-11),
10. 7702499 - Systems and methods for performing software performance estimations (2010-04-20),
11. 7673259 - System and method for synthesis reuse (2010-03-02),
12. 7634749 - Skew insensitive clocking method and apparatus (2009-12-15),
13. 7587687 - System and method for incremental synthesis (2009-09-08),
14. 7472361 - System and method for generating a plurality of models at different levels of abstraction from a single master model (2008-12-30),
15. 7069204 - Method and system for performance level modeling and simulation of electronic systems having both hardware and software elements (2006-06-27),

Title: The Innovative Journey of Luciano Lavagno

Introduction: Luciano Lavagno is a distinguished inventor based in Berkeley, CA, known for his groundbreaking contributions to the field of technology and electronics.

Latest Patents: Luciano Lavagno holds several patents in the areas of semiconductor design, embedded systems, and computer architecture, showcasing his continuous innovation and expertise in the industry.

Career Highlights: With a career spanning over two decades, Luciano Lavagno has worked with prestigious research institutions and leading technology companies, playing a pivotal role in the development of cutting-edge technologies.

Collaborations: Throughout his career, Luciano Lavagno has collaborated with top engineers, researchers, and inventors worldwide, fostering a culture of innovation and excellence in the projects he undertakes.

Conclusion: Luciano Lavagno's passion for innovation and his relentless pursuit of technological advancement have solidified his reputation as a visionary inventor in the field of electronics and semiconductor design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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