The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 27, 2006
Filed:
Sep. 28, 2000
Sherry Solden, Palo Alto, CA (US);
Edwin A. Harcourt, Townsend, MA (US);
William W. LA Rue, Jr., Leawood, KS (US);
Douglas D. Dunlop, Potomac, MD (US);
Christopher Hoover, Los Gatos, CA (US);
Qizhang Chao, Palo Alto, CA (US);
Poonam Agrawal, Sunnyvale, CA (US);
Aaron Beverly, Los Gatos, CA (US);
Massimiliano L. Chiodo, Berkeley, CA (US);
Neeti K. Bhatnagar, San Jose, CA (US);
Soumya Desai, Calcutta, IN;
Hungming Chou, Pleasanton, CA (US);
Michael D. Sholes, Redwood City, CA (US);
Sanjay Chakravarty, Delhi, IN;
Eamonn O'brien-strain, San Mateo, CA (US);
Luciano Lavagno, Berkeley, CA (US);
Sherry Solden, Palo Alto, CA (US);
Edwin A. Harcourt, Townsend, MA (US);
William W. La Rue, Jr., Leawood, KS (US);
Douglas D. Dunlop, Potomac, MD (US);
Christopher Hoover, Los Gatos, CA (US);
Qizhang Chao, Palo Alto, CA (US);
Poonam Agrawal, Sunnyvale, CA (US);
Aaron Beverly, Los Gatos, CA (US);
Massimiliano L. Chiodo, Berkeley, CA (US);
Neeti K. Bhatnagar, San Jose, CA (US);
Soumya Desai, Calcutta, IN;
Hungming Chou, Pleasanton, CA (US);
Michael D. Sholes, Redwood City, CA (US);
Sanjay Chakravarty, Delhi, IN;
Eamonn O'Brien-Strain, San Mateo, CA (US);
Luciano Lavagno, Berkeley, CA (US);
Cadence Design System, Inc., San Jose, CA (US);
Abstract
A method and system for evaluating performance level models of electronic systems having both hardware and software components is provided. The system and method allow for the simplified implementation and testing of several different architectural designs for compliance with the desired operational requirement of a designed electronic system.