Cadence Design Systems, Inc.

Esilicon Corporation

Xilinx, Inc.

Sisvel Technology S.r.l.

Institute of Computer Science, Foundation for Research and Technology- Hellas

Luciano Lavagno

Alex Kondratyev

Jordi Cortadella

Yosinori Watanabe

Dan Liu

Emre Tuncer

Patrick Charles McGeer

Alexander Saldanha

Ellen Sentovich

Mihai Teodor Lazarescu

Xin Jin

Hem C Neema

Eamonn O'Brien-Strain

Michael Jude Meyer

Christopher Edward Hoover

Neeti Khullar Bhatnagar

Vigyan Singhal

Ferran Martorell

Christos P Sotiriou

Qizhang Chao

Massimiliano L Chiodo

Alberto Sangiovanni-Vincentelli

Sherry Solden

Edwin A Harcourt

Aaron Beverly

Sanjay Chakravarty

Yoshinori Watanabe

Gai Liu

Michael D Sholes

Thomas Bollaert

Chaosheng Shi

Marcello Lajolo

William W La Rue, Jr

Douglas D Dunlop

Poonam Agrawal

Soumya Desai

Akhmareh Alireza Ramezani

Carlos Macian

Hungming Chou

Inter-kernel dataflow analysis and deadlock detection includes, for each kernel of a plurality of kernels of a design, including, using computer hardware, a signal for the kernel that is asserted in response to all processes inside the kernel stalling, wherein the plurality of kernels form a strongly connected component. For each kernel of the plurality of kernels, the signal is asserted during operation of the design in response to each process in the kernel stalling. A notification is generated indicating that the strongly connected component is deadlocked in response to each kernel of the strongly connected component asserting the signal.

Inter-kernel dataflow analysis and deadlock detection

Controlling execution of application-specific hardware pipelines includes detecting, using computer hardware, a loop construct contained in a function within a design specified in a high-level programming language, extracting, using the computer hardware, the loop construct from the function into a newly generated function of the design, and generating, using the computer hardware, a state transition graph corresponding to the loop construct. The state transition graph can be pruned by relocating operations from the function entry state and the function exit state into the loop region. A circuit design defining, at least in part, a pipeline hardware architecture implementing the loop construct can be generated using the computer hardware based, at least in part, on the pruned state transition graph.

Application-specific hardware pipeline implemented in an integrated circuit

A system for localizing an object of interest in a monitored space includes a plurality of capacitive sensors for sensing changes in the status of a space, adapted to electrically interact in a contactless way with a ground surface so as to provide a capacitance varying on the basis of such changes, and adapted to detect at least a time evolution of the capacitance and to produce a capacitance-depending signal, a filtering unit configured for reducing the noise level in the time evolution of such capacitance by filtering the capacitance-depending signal provided by the capacitive sensors, so that corresponding filtered signals are produced, and a central device in signal communication with the capacitive sensors. The central device is configured for acquiring the filtered signals of each capacitive sensor, and for determining the position of the object of interest inside the space by inferring at least a distance of the object on the basis of the filtered signals acquired from at least one of the sensors detecting the object, and by combining the at least a distance with positional data defining the positions of the plurality of capacitive sensors in the monitored space.

Capacitive sensor and method for sensing changes in a space

A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow. Exemplary circuits used in the application of the aforementioned techniques are provided. Application of mathematical models and techniques used for proving equivalence between the input description and the resulting desynchronized circuit are presented and explained.

Variability-aware scheme for high-performance asynchronous circuit voltage regulation

A circuit interconnection structure for synchronizing a network of oscillators placed on a semiconductor substrate. One such structure comprises a first synchronizing circuit electrically coupled to a second synchronizing circuit through tunable delay circuits. Also disclosed are methods to tune oscillators placed in different regions of a circuit having multiple clock domains by estimating the relative slack of a first group of signals within the circuit with regard to the period of a first clock domain, and estimating the relative slack of the second group of signals within the circuit with regard to the period of second clock domain, wherein the estimating is performed at process and operational corners that cover the variability of the circuit at different speed conditions, then calculating tuning values for the oscillator delays for each region such that the oscillator delay slack matches the worst relative slack of the signals of the same region.

Network of tightly coupled performance monitors for determining the maximum frequency of operation of a semiconductor IC

Apparatus and methods for clock domain crossing between a first clock domain and a second clock domain. The apparatus comprises a first control logic element for processing a handshake signal and producing a first arbiter input signal. Concurrently a second control logic element processes a second handshake signal and produces a second arbiter input signal. Exemplary embodiments include exactly one arbiter element inputting the first arbiter input signal, inputting the second arbiter input signal, outputting a first clocking signal to the first sequential element and outputting a second clocking signal to the second sequential element. For managing metastability by controlling the timing of the clocking inputs of the sequential devices, the apparatus includes a first controllable lock delay element selected to satisfy the setup constraint of the second sequential element, and a second controllable lock delay element selected to satisfy the hold constraint of the second sequential element.

Asynchronous scheme for clock domain crossing

A method of synthesis of multiple implementations of a design is provided comprising: translating a model of the design to a first output model compliant with first constraints; and translating the model of the design to a second output model compliant with second constraints.

System and method for synthesis reuse

A combined language-compiler that provides for the efficient compilation process of hybrid computer code written using a plurality of computer languages by splitting the hybrid code in such a way that each code statement is optimally independently compliable. The designer specifies both computation and communication between different hybrid code modules.

Method and system for split-compiling a hybrid language program

A method of converting a Boolean logic circuit into an asynchronous multi-rail circuit is provided. A Boolean logic circuit is converted into a first multi-rail circuit using at least Shannon's expansion. The first multi-rail circuit is technology mapped into a second multi-rail circuit. Completion detection circuitry is added which receives the primary outputs of the second multi-rail circuit.

Asynchronous, multi-rail, asymmetric-phase, static digital logic with completion detection and method for designing the same

Systems and methods are provided for annotating software with performance information. The computer code is compiled into assembler code, the assembler code is translated into a simulation model, expressed in assembler-level source code. The simulation model is annotated with information for calculating various performance parameters of the software, such as timing information, or resource usage information. The simulation model is then re-compiled and executed on a simulator, optionally including a hardware simulation model, and the performance information is computed from the simulation.

Systems and methods for performing software performance estimations

A method of designing a skew insensitive circuit is performed by designing a synchronous circuit including flip-flops and combinatorial logic and, for each flip-flop, inserting logic gates to receive a skewed clock signal and to locally derive non-overlapping clock phases from the skewed clock signal.

Skew insensitive clocking method and apparatus

A method of synthesis of a model representing a design is provided comprising: inputting to a synthesis tool information representing a design at a level of abstraction; using a synthesis tool to automatically translate the information representing a design at a level of abstraction to a model representing the design at a lower level abstraction; and producing a record the information input to the tool representing the design at the level of abstraction.

System and method for incremental synthesis

A method of producing multiple models of a hardware (integrated circuit) design including: translating a master model of a design of the integrated circuit to at least first and second models that are functionally equivalent to the master model and that are at different levels of abstraction from each, other and in which each of the first and second models includes integrated circuit timing information that is accurate for its level of abstraction.

System and method for generating a plurality of models at different levels of abstraction from a single master model

A method and system for evaluating performance level models of electronic systems having both hardware and software components is provided. The system and method allow for the simplified implementation and testing of several different architectural designs for compliance with the desired operational requirement of a designed electronic system.

Method and system for performance level modeling and simulation of electronic systems having both hardware and software elements

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Berkeley, CA, United States of America

Luciano Lavagno