Santa Clara, CA, United States of America

Luca Gaetano Amaru

This inventor holds 9 USPTO granted patents and 4 published patent applications. Top assignee: Synopsys, Inc.. Active years: 2018-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Luca Gaetano Amaru. Retrieved from https://idiyas.com/inventor/luca-gaetano-amaru

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 9 

% Patents Active = 88.9

Average Co-Inventor Count = 3.7

ph-index = 1

Forward Citations = 6(Granted Patents)


Company Filing History:


Years Active: 2018-2026

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9 patents (USPTO):Explore Patents

Title: Innovations by Luca Gaetano Amaru

Introduction

Luca Gaetano Amaru is a prominent inventor based in Santa Clara, CA (US). He has made significant contributions to the field of integrated circuit design, holding a total of 9 patents. His work focuses on enhancing the efficiency and performance of logical circuit designs.

Latest Patents

One of his latest patents is titled "Fast synthesis of logical circuit design with predictive timing." This invention involves a system that receives a logic design of a circuit for an integrated circuit and applies a reduced synthesis process. This process is less computation-intensive compared to the optimized digital implementation synthesis process and generates a netlist with suboptimal delay. The system then provides this generated netlist as input to a timing analysis that alters the standard delay computation to predict the timing of a fully optimized netlist. The reduced synthesis process boasts a faster execution time while maintaining comparable performance, power, and area within a threshold of results generated using optimized digital implementation synthesis processes.

Another notable patent is "Application-specific integrated circuit (ASIC) synthesis based on lookup table (LUT) mapping and optimization." In this invention, a logic network for an integrated circuit is synthesized by mapping the logic network to a network of lookup tables (LUTs). The LUT mapping is based on estimated areas of the LUTs, and the individual LUTs are improved using various Boolean optimization techniques. The network of improved LUTs is then reduced to a gate-level netlist of standard cells.

Career Highlights

Luca Gaetano Amaru is currently employed at Synopsys, Inc., where he continues to innovate in the field of integrated circuit design. His work has significantly impacted the efficiency of circuit synthesis processes.

Collaborations

Luca has collaborated with notable colleagues, including Patrick Vuillod and Jiong Luo, who contribute to his innovative projects.

Conclusion

Luca Gaetano Amaru's contributions to integrated circuit design through his patents demonstrate his commitment to advancing technology in this field. His innovative approaches continue to influence the efficiency and performance of logical circuit designs.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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