Application-specific integrated circuit (asic) synthesis based on lookup table (lut) mapping and optimization

Abstract

Some aspects utilize an iterative process to synthesis a logic network within an ASIC using lookup table (LUT) optimization techniques. The logic network may be represented by an And-Inverter graph (AIG), as described in more detail below. On each iteration, the current AIG representation of the logic network is mapped to a network of k-LUTs. A k-LUT is a lookup table that can represent any function of k variables. This network may then be improved using LUT optimization techniques. The improved network of k-LUTs is decomposed into a trial AIG representation, which may be further improved for example by applying Boolean-based optimization techniques. The current AIG representation may then be updated in accordance with the quality of the trial AIG representation produced by the current iteration. The final AIG representation from the iterations is synthesized to a netlist of standard cells.