Fremont, CA, United States of America

Jiong Luo


Average Co-Inventor Count = 3.7

ph-index = 1

Forward Citations = 6(Granted Patents)


Location History:

  • Fremont, CA (US) (2018 - 2021)
  • Mountain View, CA (US) (2023)

Company Filing History:


Years Active: 2018-2024

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8 patents (USPTO):Explore Patents

Title: Innovations of Jiong Luo in Integrated Circuit Design

Introduction

Jiong Luo is a prominent inventor based in Fremont, CA, known for his significant contributions to the field of integrated circuit design. With a total of 8 patents to his name, he has made remarkable advancements that enhance the efficiency and performance of electronic systems.

Latest Patents

One of Jiong Luo's latest patents is titled "Fast synthesis of logical circuit design with predictive timing." This innovative system receives a logic design of a circuit of an integrated circuit and applies a reduced synthesis process to the logical design. The reduced synthesis process is less computation-intensive compared to the optimized digital implementation synthesis process and generates a netlist with suboptimal delay. The system provides the generated netlist as input to a timing analysis that alters the standard delay computation through scaling and other means to predict the timing of a fully optimized netlist. This reduced synthesis process has a faster execution time compared to the optimized digital implementation synthesis process while maintaining comparable performance, power, and area within a threshold of the results generated using the optimized digital implementation synthesis process.

Another notable patent is "Application-specific integrated circuit (ASIC) synthesis based on lookup table (LUT) mapping and optimization." In this patent, a logic network for an integrated circuit is synthesized by mapping the logic network to a network of lookup tables (LUTs). The LUT mapping is based on estimated areas of the LUTs, and the individual LUTs in the network are improved using various Boolean optimization techniques. The network of improved LUTs is then reduced to a gate-level netlist of standard cells.

Career Highlights

Jiong Luo is currently employed at Synopsys, Inc., where he continues to innovate and develop cutting-edge solutions in integrated circuit design. His work has significantly impacted the efficiency and effectiveness of electronic systems.

Collaborations

Throughout his career, Jiong has collaborated with talented individuals such as Luca Gaetano Amaru and Patrick Vuillod, contributing to various projects that push the boundaries of technology.

Conclusion

Jiong Luo's contributions to integrated circuit design through his innovative patents and collaborations highlight his role as a leading inventor in the field. His work continues to influence the development of more efficient electronic systems.

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