The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 2021

Filed:

Aug. 30, 2019
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Luca Gaetano Amaru, Santa Clara, CA (US);

Eleonora Testa, Renens, CH;

Patrick Vuillod, St. Bernard du Touvet, FR;

Jiong Luo, Fremont, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/00 (2020.01); G06F 30/20 (2020.01); G06F 30/25 (2020.01); G06F 30/327 (2020.01);
U.S. Cl.
CPC ...
G06F 30/20 (2020.01); G06F 30/25 (2020.01); G06F 30/327 (2020.01);
Abstract

Techniques and systems for optimizing a logic network are described. Some embodiments automatically identify scenarios where Boolean methods are best driven by truth tables, binary decision diagrams (BDDs) or satisfiability (SAT). Some embodiments use circuit partitioning techniques that are based on hash-tables and topological sorting, and that are capable of grouping nodes with high simplification likelihood and still are able to efficiently scale to large circuits. Some embodiments feature a generalized resubstitution framework based on computing, and implementing, the Boolean difference between two nodes. Some embodiments include enhancements to (i) gradient-based and-inverter-graph (AIG) optimization, (ii) heterogeneous elimination for kerneling, and (iii) revisitation of maximum set of permissible functions (MSPF) computation with BDDs.


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