San Jose, CA, United States of America

Lidia Daldoss

This inventor holds 2 USPTO granted patents. Top assignee: Pdf Solutions, Incorporated. Active years: 2006-2010.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Lidia Daldoss. Retrieved from https://idiyas.com/inventor/lidia-daldoss-bzt6w3um

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 50.0

Average Co-Inventor Count = 4.0

ph-index = 2

Forward Citations = 20(Granted Patents)


Company Filing History:


Years Active: 2006-2010

Loading Chart...
2 patents (USPTO):Explore Patents

Title: Lidia Daldoss: Innovator in Semiconductor Technology

Introduction

Lidia Daldoss is a prominent inventor based in San Jose, CA (US). She has made significant contributions to the field of semiconductor technology, holding 2 patents that showcase her innovative approach to improving device performance.

Latest Patents

One of her latest patents is titled "Method for reducing layout printability effects on semiconductor device performance." This patent involves performing a printability simulation on a mask layout across various lithography process conditions. It identifies layout configurations that could lead to functional or parametric failures in semiconductor devices. The process includes obtaining a test structure representative of the identified layout configuration and defining a design of experiment to investigate the effects of variations in layout attributes. Multiple instances of the test structure are fabricated on a wafer, and their electrical performance characteristics are measured to determine layout attributes that may cause failures.

Another notable patent is the "Methodology for the optimization of testing and diagnosis of analog and mixed signal ICs and embedded cores." This method analyzes integrated circuits (ICs) that include both digital and analog components. It ensures that the IC meets various performance specifications while monitoring fabrication by measuring process factors and a defined set of electrical test variables. The methodology involves forming linearly independent electrical test parameters and mapping process factors to these parameters, ultimately enabling the modeling of IC performance.

Career Highlights

Lidia Daldoss is currently employed at Pdf Solutions, Incorporated, where she continues to advance her research and development efforts in semiconductor technology. Her work has been instrumental in enhancing the reliability and performance of integrated circuits.

Collaborations

Some of her notable coworkers include Sharad Saxena and Patrick D McNamara, with whom she collaborates on various projects within the semiconductor industry.

Conclusion

Lidia Daldoss is a trailblazer in the semiconductor field, with her innovative patents contributing to the advancement of technology. Her work at Pdf Solutions, Incorporated, along with her collaborations, underscores her commitment to improving device performance and reliability.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…