Pdf Solutions, Incorporated

Lidia Daldoss

Sharad Saxena

Rakesh Vallishayee

Carlo Guardiani

Christoph Dolainsky

Patrick D McNamara

A printability simulation is performed on a mask layout over a range of lithography process conditions. A layout configuration capable of inducing functional or parametric failure in a semiconductor device is identified in the mask layout. A test structure representative of the identified layout configuration is obtained. A design of experiment is associated with the test structure. The design of experiment is defined to investigating effects of variations of one or more layout attributes in the test structure. Multiple instance of the test structure are fabricated on a wafer according to the design of experiment. Electrical performance characteristics of the fabricated test structures are measured. Based on the measured electrical performance characteristics, one or more layout attributes of the test structure capable of causing functional or parametric failure are determined.

Method for reducing layout printability effects on semiconductor device performance

A method for analyzing an integrated circuit (IC) having at least one of the group consisting of digital and analog components, where the IC is designed to meet a plurality of circuit performance specifications, and fabrication of the IC is monitored by measuring process factors and a previously defined set of electrical test variables. A set of linearly independent electrical test parameters are formed based on a subset of the set of electrical test variables. The set of process factors is mapped to the linearly independent electrical test parameters. A plurality of figure-of-merit (FOM) performance models are formed based on the process factors. The FOM models are combined with the mapping to enable modeling of IC performance based on the linearly independent electrical test parameters.

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Lidia Daldoss