The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 05, 2010
Filed:
Sep. 29, 2006
Lidia Daldoss, San Jose, CA (US);
Sharad Saxena, Richardson, TX (US);
Christoph Dolainsky, Wessling, DE;
Rakesh R. Vallishayee, San Jose, CA (US);
Lidia Daldoss, San Jose, CA (US);
Sharad Saxena, Richardson, TX (US);
Christoph Dolainsky, Wessling, DE;
Rakesh R. Vallishayee, San Jose, CA (US);
PDF Solutions, Inc., San Jose, CA (US);
Abstract
A printability simulation is performed on a mask layout over a range of lithography process conditions. A layout configuration capable of inducing functional or parametric failure in a semiconductor device is identified in the mask layout. A test structure representative of the identified layout configuration is obtained. A design of experiment is associated with the test structure. The design of experiment is defined to investigating effects of variations of one or more layout attributes in the test structure. Multiple instance of the test structure are fabricated on a wafer according to the design of experiment. Electrical performance characteristics of the fabricated test structures are measured. Based on the measured electrical performance characteristics, one or more layout attributes of the test structure capable of causing functional or parametric failure are determined.