The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2006
Filed:
Jan. 09, 2003
Sharad Saxena, Richardson, TX (US);
Patrick D. Mcnamara, San Jose, CA (US);
Carlo Guardiani, San Jose, CA (US);
Lidia Daldoss, San Jose, CA (US);
Sharad Saxena, Richardson, TX (US);
Patrick D. McNamara, San Jose, CA (US);
Carlo Guardiani, San Jose, CA (US);
Lidia Daldoss, San Jose, CA (US);
PDF Solutions, Inc., San Jose, CA (US);
Abstract
A method for analyzing an integrated circuit (IC) having at least one of the group consisting of digital and analog components, where the IC is designed to meet a plurality of circuit performance specifications, and fabrication of the IC is monitored by measuring process factors and a previously defined set of electrical test variables. A set of linearly independent electrical test parameters are formed based on a subset of the set of electrical test variables. The set of process factors is mapped to the linearly independent electrical test parameters. A plurality of figure-of-merit (FOM) performance models are formed based on the process factors. The FOM models are combined with the mapping to enable modeling of IC performance based on the linearly independent electrical test parameters.