Hsinchu, Taiwan

Kuo-Chin Hsu

This inventor holds 3 USPTO granted patents and 1 published patent application. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 1995-2001.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kuo-Chin Hsu. Retrieved from https://idiyas.com/inventor/kuo-chin-hsu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 3 

% Patents Active = 100.0

Average Co-Inventor Count = 2.6

ph-index = 3

Forward Citations = 105(Granted Patents)


Company Filing History:


Years Active: 1995-2001

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3 patents (USPTO):Explore Patents

Title: Kuo-Chin Hsu: Innovator in Semiconductor Technology

Introduction

Kuo-Chin Hsu is a prominent inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of 3 patents. His work focuses on innovative processes that enhance the efficiency and effectiveness of semiconductor devices.

Latest Patents

One of Hsu's latest patents is an "Integrated method of damascene and borderless via process." This new process provides a method to create openings and interconnect patterns for dual damascene structures. The process involves sequentially depositing four layers of dielectric over a pattern of interconnect metal. The via hole pattern is defined first, followed by the interconnect line pattern. The via pattern is etched through the upper layer of dielectric and the stop layer, utilizing only one etch processing step to create the desired vias and interconnect line pattern. After the patterns are created, a barrier layer is blanket deposited, metal is added for the dual damascene structure, and the interconnect line pattern is polished.

Another significant patent is the "LDD method of coding mask ROM device and LDD coded mask ROM device." This invention involves forming a CMOS Mask ROM semiconductor device in the P-well NMOS region of a silicon semiconductor substrate. The method includes forming gate oxide over the substrate, creating a control gate layer, and patterning a gate electrode through etching. The process also involves forming an LDD mask, ion implanting P-type and N-type dopants, and creating self-aligned regions that enhance the device's performance.

Career Highlights

Kuo-Chin Hsu is currently employed at Taiwan Semiconductor Manufacturing Company Ltd. His work at this leading semiconductor manufacturer has allowed him to contribute to cutting-edge technologies in the industry. His innovative approaches have positioned him as a key figure in semiconductor advancements.

Collaborations

Hsu has collaborated with notable colleagues, including John C-s Wei and An-Min Chiang. These partnerships have fostered a collaborative environment that encourages innovation and the sharing of ideas within the semiconductor field.

Conclusion

Kuo-Chin Hsu's contributions to semiconductor technology through his patents and collaborations highlight his role as an influential inventor. His innovative methods continue to shape the future of semiconductor manufacturing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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