Taiwan Semiconductor Manufacturing Comp. Ltd.

Kuo-Chin Hsu

An-Min Chiang

Meng-Chang Liu

John C-s Wei

Yen-Long Chiu

Chao-Bao Cheng

A new process is provided to create openings and interconnect patterns for the dual damascene structure. Four layers of dielectric are sequentially deposited over a pattern of interconnect metal. The via hole pattern is defined, the interconnect line pattern is next defined. The via pattern is etched though the upper layer of dielectric and through the stop layer. Only one etch processing step is used to create the desired vias and the desired interconnect line pattern. After the interconnect patterns and vias have been created in the four layers of dielectric, a barrier layer is blanket deposited, the metal is deposited for the dual damascene structure and the interconnect line pattern and polished.

Integrated method of damascene and borderless via process

A CMOS Mask ROM semiconductor device is formed in P-well NMOS region of a silicon semiconductor substrate with FOX regions on the surface thereof. A method of forming the device includes forming gate oxide over the substrate between FOX regions; forming a control gate layer over the gate oxide. Then form a gate mask over the device with and pattern a gate electrode and the gate oxide layer by etching through mask openings. Next, form an LDD mask over the device exposing the gate. Ion implant a P type dopant of a first dosage level through mask openings forming reverse type LDD implant doped P type regions. Form spacers adjacent to the electrode over the substrate. Ion implant an N type dopant of a second dosage level through the opening in the mask and aside from the spacers and the electrode into exposed portions of the substrate. The N type doped regions are thus self-aligned with the spacers and the gate and they provide a second dosage level in the substrate, the second dosage level being substantially different from the first dosage level.

LDD method of coding mask ROM device and LDD coded mask ROM device

A new method of metal etching using a disposable metal antireflective coating process along with metal dry/wet etching is described. An insulating layer is provided over semiconductor device structures in and on a semiconductor substrate. Openings are made through the insulating layer to the semiconductor substrate and to the semiconductor device structures to be contacted. A barrier metal layer is deposited conformally over the insulating layer and within the openings. A metal layer is deposited over the barrier metal layer. The metal layer is covered with an antireflective coating. A layer of photoresist is coated onto the substrate and patterned to provide a photoresist mask. The antireflective coating, the metal layer and a portion of the barrier metal layer are etched away where the layers are not covered by the photoresist mask. The photoresist mask is removed. The remaining barrier metal layer not covered by the patterned metal layer is etched away whereby all the remaining antireflective coating is also removed completing the metal patterning in the fabrication of the integrated circuit.

Growing community of inventors

Hsin-Chu, Taiwan

Kuo-Chin Hsu