Kiyohiko Sakakibara

This inventor holds 32 USPTO granted patents and 1 published patent application, primarily in Three-Dimensional Memory Devices. Top assignee: Sandisk Technologies Inc.. Active years: 2016-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kiyohiko Sakakibara. Retrieved from https://idiyas.com/inventor/kiyohiko-sakakibara

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 32 (Patent Applications = 1)

% Patents Active = 93.8

Average Co-Inventor Count = 2.5

ph-index = 11

Forward Citations = 415(Granted Patents)

Location History:

Yokkaichi, JP (2016 - 2023)
Mie, JP (2021 - 2023)

Company Filing History:

32 out of 4,966

Sandisk Technologies Inc.

patents

Years Active: 2016-2026

Loading Chart...

Areas of Expertise:

Three-Dimensional Memory

Boosting Read Scheme

Threshold Voltage

BiCS Device Structure

Charge Storage Regions

Memory Stack Structures

Vertical Transistors

Dielectric Layer

Nitrided Direct Source

Capped Insulating Source

Carbon-Doped Source

Self-Aligned Conductive Strips

32 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12640171 - Buried source line structure for boosting read scheme (2026-05-26),

2. 11763907 - Reverse VT-state operation and optimized BiCS device structure (2023-09-19),

3. 11631691 - Three-dimensional flat memory device including a dual dipole blocking dielectric layer and methods of making the same (2023-04-18),

4. 11456044 - Reverse VT-state operation and optimized BiCS device structure (2022-09-27),

5. 11348649 - Threshold voltage setting with boosting read scheme (2022-05-31),

6. 11342006 - Buried source line structure for boosting read scheme (2022-05-24),

7. 11227663 - Boosting read scheme with back-gate bias (2022-01-18),

8. 11004518 - Threshold voltage setting with boosting read scheme (2021-05-11),

9. 10957401 - Boosting read scheme with back-gate bias (2021-03-23),

10. 10950311 - Boosting read scheme with back-gate bias (2021-03-16),

11. 10916556 - Three-dimensional memory device using a buried source line with a thin semiconductor oxide tunneling layer (2021-02-09),

12. 10903222 - Three-dimensional memory device containing a carbon-doped source contact layer and methods for making the same (2021-01-26),

13. 10854627 - Three-dimensional memory device containing a capped insulating source line core and method of making the same (2020-12-01),

14. 10777575 - Three-dimensional memory device with self-aligned vertical conductive strips having a gate-all-around configuration and method of making the same (2020-09-15),

15. 10720445 - Three-dimensional memory device having nitrided direct source strap contacts and method of making thereof (2020-07-21),

Title: Innovations by Kiyohiko Sakakibara: A Leader in Non-Volatile Memory Technology

Introduction

Kiyohiko Sakakibara, hailing from Yokkaichi, Japan, is a prominent inventor known for his significant contributions to the field of non-volatile memory technology. With a remarkable portfolio of 31 patents, he has consistently pushed the boundaries of innovation and has played a crucial role in advancing memory device architecture.

Latest Patents

Sakakibara's most recent patents showcase innovative methods for improving the reliability of non-volatile memory. One of his notable inventions includes a reverse VT-state operation and an optimized BiCS device structure. This invention describes systems and methods that aim to reduce the number of memory cell transistors experiencing excessive hole injection. By reversing the programmed data states of the memory cell transistors, the design addresses the challenge of maintaining the threshold voltage below a negative threshold, ultimately enhancing memory reliability. Another remarkable patent involves a three-dimensional flat memory device that integrates a dual dipole blocking dielectric layer. This device incorporates alternating stacks of insulating and electrically conductive strips, optimizing the arrangement of memory stack structures for improved efficiency.

Career Highlights

Throughout his career at SanDisk Technologies Inc., Kiyohiko Sakakibara has demonstrated exceptional expertise in the development of advanced memory technologies. His innovative approaches have led to breakthroughs that not only enhance performance but also ensure the reliability of non-volatile memory systems. His contributions have established him as a leading figure in the field and reflect his commitment to technological advancement.

Collaborations

Sakakibara's achievements have been bolstered by collaborative efforts with esteemed colleagues, including Zhixin Cui and Masaaki Higashitani. Together, they have worked on various projects that explore new frontiers in memory technology, facilitating the growth and development of new solutions within the industry.

Conclusion

Kiyohiko Sakakibara's extensive work in the domain of non-volatile memory has significantly shaped the landscape of modern memory devices. His inventive spirit and forward-thinking approach have not only resulted in a substantial number of patents but have also paved the way for future innovations in the technology sector. As he continues to contribute to advancements in memory technology, Sakakibara remains a pivotal figure in the pursuit of innovation.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

1 patent pending: