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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12640171 B1

PDFFull Text
Date of Patent:
May. 26, 2026

Filed:

Apr. 28, 2022

Buried source line structure for boosting read scheme

Applicant:

Sandisk Technologies, Inc., Milpitas, CA (US);

Inventors:

Kiyohiko Sakakibara, Mie, JP;

Ken Oowada, Fujisawa, JP;

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:

PEARL COHEN ZEDEK LATZER BARATZ LLP

Primary Examiner:

Marcos D Pizarro

Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
G11C 5/063 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10D 84/0128 (2025.01); H10D 84/016 (2025.01); H10D 84/038 (2025.01); H10D 84/8311 (2025.01); H10D 84/837 (2025.01);
Abstract

A non-volatile memory device is provided that includes an alternating stack of conducting layers and dielectric layers, a charge trap layer, a layer of polysilicon, and a tunneling dielectric layer arranged between the charge trap layer and the layer of polysilicon. The charge trap layer extends through the alternating stack of conducting layers and dielectric layers. The layer of polysilicon includes a first portion having a first thickness and a second portion having a second thickness that is greater than the first thickness. The second portion is arranged below the alternating stack of conducting layers and dielectric layers.

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