The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2021

Filed:

Nov. 26, 2018
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Kiyohiko Sakakibara, Yokkaichi, JP;

Takumi Moriyama, Yokkaichi, JP;

Yu-Hsien Hsu, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/1157 (2017.01); H01L 27/11582 (2017.01); H01L 27/11556 (2017.01); H01L 29/22 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1157 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); H01L 29/22 (2013.01); H01L 29/4234 (2013.01); H01L 29/42328 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01);
Abstract

A three-dimensional memory device includes a source-level material layer stack located over a substrate that includes, from bottom to top, a lower source-level semiconductor layer, a semiconductor oxide tunneling layer, a source contact layer including a doped semiconductor material, and an upper source-level semiconductor layer, an alternating stack of electrically conductive layers and insulating layers located over the source-level material layer stack, and memory stack structures that extend through the alternating stack and into an upper portion of the lower source-level semiconductor layer, in which each memory stack structure includes a vertical semiconductor channel and a memory film laterally surrounding the vertical semiconductor channel, and each of the vertical semiconductor channels vertically extends through, and is electrically connected to, the source contact layer.


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