The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2020

Filed:

Sep. 28, 2018
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Satoshi Shimizu, Yokkaichi, JP;

Takumi Moriyama, Yokkaichi, JP;

Kiyohiko Sakakibara, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01); H01L 27/11565 (2017.01); H01L 29/423 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 27/11526 (2017.01); H01L 27/11519 (2017.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 23/5226 (2013.01); H01L 23/53295 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01); H01L 29/4234 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11526 (2013.01); H01L 27/11556 (2013.01);
Abstract

A lower source-level semiconductor layer, a sacrificial semiconductor layer, an upper source-level semiconductor layer, and an alternating stack of insulating layers and sacrificial material layers are sequentially formed over a substrate. An array of memory stack structures containing vertical semiconductor channels that extend through the alternating stack and into an upper portion of the lower source-level semiconductor layer is formed. A backside trench is formed through the alternating stack, and a source cavity is formed by removing the sacrificial semiconductor layer. A doped source contact layer is formed on each of the vertical semiconductor channels in the source cavity. A silicon nitride liner is formed on the doped source contact layer. The sacrificial material layers are replaced with electrically conductive layers. A dielectric wall structure is formed in the backside trench.


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