Palo Alto, CA, United States of America

Kerem Akarvardar

This inventor holds 3 USPTO granted patents and 1 published patent application. Top assignees: California Institute of Technology, Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2009-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kerem Akarvardar. Retrieved from https://idiyas.com/inventor/kerem-akarvardar-wlz3l04y

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 3 

% Patents Active = 33.3

Average Co-Inventor Count = 6.3

ph-index = 2

Forward Citations = 6(Granted Patents)


Location History:

  • Grenoble Cedex, FR (2009)
  • Palo Alto, CA (US) (2011)

Company Filing History:


Years Active: 2009-2024

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3 patents (USPTO):Explore Patents

Title: Innovations of Kerem Akarvardar

Introduction

Kerem Akarvardar is an accomplished inventor based in Palo Alto, CA. He holds a total of 3 patents that showcase his expertise in semiconductor technology and analog circuits. His innovative contributions have made a significant impact in the field of electronics.

Latest Patents

One of his latest patents is a semiconductor structure and method of manufacture. This patent describes a semiconductor structure that includes a first dielectric layer, an electrode within the first dielectric layer, a second dielectric layer in the electrode, and a phase change material over the first dielectric layer, the electrode, and the second dielectric layer. The design ensures that the uppermost surface of the electrode is positioned above the surfaces of the dielectric layers or the lowermost surface of the phase change material.

Another notable patent is the four-gate transistor analog multiplier circuit. This invention utilizes a differential output analog multiplier circuit that employs four G-FETs, with each source connected to a current source. The G-FETs are organized into two pairs, where one pair connects its drains to a load, while the other pair connects to a different load. The differential output voltage is derived from these two loads, with specific configurations for input voltages applied to the gates of the G-FETs.

Career Highlights

Kerem has worked with prestigious institutions such as the California Institute of Technology and Taiwan Semiconductor Manufacturing Company. His experience in these organizations has contributed to his development as a leading inventor in the semiconductor field.

Collaborations

Throughout his career, Kerem has collaborated with notable professionals, including Mohammad Mehdi Mojarradi and Benjamin J Blalock. These collaborations have further enriched his work and innovations.

Conclusion

Kerem Akarvardar's contributions to semiconductor technology and analog circuits reflect his innovative spirit and expertise. His patents demonstrate a commitment to advancing technology in meaningful ways.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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