The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 30, 2011
Filed:
May. 21, 2007
Mohammad M. Mojarradi, La Canada, CA (US);
Benjamin Blalock, Knoxville, TX (US);
Sorin Cristoloveanu, Seyssinet-Pariset, FR;
Suheng Chen, Knoxville, TN (US);
Kerem Akarvardar, Palo Alto, CA (US);
Mohammad M. Mojarradi, La Canada, CA (US);
Benjamin Blalock, Knoxville, TX (US);
Sorin Cristoloveanu, Seyssinet-Pariset, FR;
Suheng Chen, Knoxville, TN (US);
Kerem Akarvardar, Palo Alto, CA (US);
California Institute of Technology, Pasadena, CA (US);
Abstract
A differential output analog multiplier circuit utilizing four G-FETs, each source connected to a current source. The four G-FETs may be grouped into two pairs of two G-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.