The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2009
Filed:
Mar. 15, 2006
Amir Fijany, Pasadena, CA (US);
Farrokh Vatan, West Hills, CA (US);
Kerem Akarvardar, Grenoble Cedex, FR;
Benjamin Blalock, Knoxville, TN (US);
Suheng Chen, Knoxville, TN (US);
Sorin Cristoloveanu, Grenoble Cedex, FR;
Elzbieta Kolawa, Bradbury, CA (US);
Mohammad M. Mojarradi, La Canada, CA (US);
Nikzad Toomarian, Pasadena, CA (US);
Amir Fijany, Pasadena, CA (US);
Farrokh Vatan, West Hills, CA (US);
Kerem Akarvardar, Grenoble Cedex, FR;
Benjamin Blalock, Knoxville, TN (US);
Suheng Chen, Knoxville, TN (US);
Sorin Cristoloveanu, Grenoble Cedex, FR;
Elzbieta Kolawa, Bradbury, CA (US);
Mohammad M. Mojarradi, La Canada, CA (US);
Nikzad Toomarian, Pasadena, CA (US);
California Institute of Technology, Pasadena, CA (US);
Abstract
An universal and programmable logic gate based on G-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G-FET is also presented. The G-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.