Tokyo, Japan

Keiichi Yoshizumi

This inventor holds 25 USPTO granted patents, primarily in Semiconductor Technology. Top assignees: Hitachi, Ltd., Renesas Technology Corp., Hitachi Ulsi Engineering Corp.. Active years: 1991-2012.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Keiichi Yoshizumi. Retrieved from https://idiyas.com/inventor/keiichi-yoshizumi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 52.0

Average Co-Inventor Count = 4.8

ph-index = 7

Forward Citations = 154(Granted Patents)


Location History:

  • Kokubungi, JP (1994)
  • Hamura, JP (2003 - 2004)
  • Kokubunji, JP (1991 - 2006)
  • Hitachinaka, JP (2007 - 2009)
  • Tokyo, JP (2008 - 2012)

Company Filing History:


Years Active: 1991-2012

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Areas of Expertise:
Semiconductor Device
Ferroelectric Memory
Integrated Circuit
High Breakdown Voltage
Manufacturing Process
Capacitance Element
MISFET
Memory Device
Doping Method
Field Effect Transistor
Protection Electrode
25 patents (USPTO):Explore Patents

Title: Innovator Profile: Keiichi Yoshizumi

Introduction

Keiichi Yoshizumi is a notable inventor based in Tokyo, Japan, recognized for his significant contributions to the field of semiconductor technology. With a remarkable portfolio that includes 25 patents to his name, Yoshizumi has made strides that enhance the efficiency and performance of semiconductor devices.

Latest Patents

Among his latest innovations is a patent for a semiconductor device and a method of manufacturing the same. This innovative semiconductor device is designed to eliminate the need for a larger chip area, even with the existence of a dummy active region. It improves the surface flatness of the semiconductor substrate, which is crucial for the reliability of electronic components. The manufacturing process involves creating a thick gate insulating film for a high-voltage Metal-Insulator-Semiconductor Field-Effect Transistor (MISFET) over an n-type buried layer serving as an active region. Notably, a resistance element is formed over this gate insulating film, reducing the coupling capacitance between the substrate and the resistance element, thus enhancing overall performance.

Career Highlights

Keiichi Yoshizumi has had a distinguished career at several influential technology companies, including Hitachi, Ltd. and Renesas Technology Corporation. His work has consistently focused on advancing semiconductor technologies, contributing to the development of more efficient and compact electronic components.

Collaborations

Throughout his career, Yoshizumi has collaborated with esteemed colleagues, including Hisayuki Kato and Kazufumi Suenaga. Together, they have shared insights and expertise, driving innovation in semiconductor research and applications.

Conclusion

Keiichi Yoshizumi exemplifies the spirit of innovation in the semiconductor industry. His extensive patent portfolio highlights his commitment to advancing technology and improving electronic device performance. As he continues to work and innovate, his contributions will undoubtedly leave a lasting impact on the field.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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