Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Ulsi Engineering Corp.

Renesas Electronics Corporation

Hitachi Engineering Co., Ltd.

Keiichi Yoshizumi

Hisayuki Kato

Kiyoshi Ogata

Hideki Yasuoka

Masami Koketsu

Kazuhiko Horikoshi

Kazufumi Suenaga

Shuji Ikeda

Hisahiko Abe

Jun Tanaka

Kazushi Fukuda

Masahito Yamazaki

Yasuko Yoshida

Kazuhisa Higuchi

Soichiro Hashiba

Fumiyuki Kanai

Takayuki Nakaji

Takashi Hashimoto

Toshiaki Yamanaka

Kousuke Okuyama

Shinji Nishihara

Satoshi Kudo

Yasuhiro Takeda

Kunihiko Kato

Mitsuhiro Mori

Shigeya Toyokawa

Kazuo Yoshizaki

Kazushi Tomita

Tsuyoshi Tabata

Koichi Imato

Satoru Haga

Chiemi Hashimoto

Hiromichi Waki

Kohji Yamasaki

Motoko Kawashima

Junichi Takano

Mitsugu Oshima

Kazuo Yano

Mitsuru Hiraki

Masataka Minami

Atsuo Watanabe

Naotaka Hashimoto

Yutaka Hoshino

Takahiro Nagano

Kazushige Sato

Kyoichiro Asayama

Makoto Saeki

Ryuichi Izawa

Kouichi Seki

Kiyoshi Nagai

Takeshi Fukazawa

Eri Okamoto

Seiichi Ariga

Kiichi Makuta

Yuuki Koide

A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.

Semiconductor device and a method of manufacturing the same

With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, ntype semiconductor regions, each having a conduction type opposite to ptype semiconductor regions for a source and drain of a high breakdown voltage pMIS, are disposed in a boundary region between each of trench type isolation portions at both ends, in a gate width direction, of a channel region of the high breakdown voltage pMIS and a semiconductor substrate at positions spaced away from ptype semiconductor regions, each having a field relaxing function, of the high breakdown voltage pMIS, so as not to contact the ptype semiconductor regions (on the drain side, in particular). The ntype semiconductor regions extend to positions deeper than the trench type isolation portions.

Semiconductor device with MISFET that includes embedded insulating film arranged between source/drain regions and channel

A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device.

Method of manufacturing a semiconductor device that includes a process for forming a high breakdown voltage field effect transistor

The present invention is a high quality semiconductor memory device using a ferroelectric thin film capacitor as a memory capacitor at a high manufacturing yield, the ferroelectric thin film of the capacitor is specified such that the relative standard deviation of crystal grain sizes is 13% or less, to thereby ensure a high remanent polarization value and a small film fatigue (large rewritable number).

Semiconductor memory device and manufacturing method thereof

A long life ferroelectric memory device using a thin ferroelectric film capacitor as a memory capacitor is obtained by disposing a plurality of degradation preventive layers on an upper protection electrode and an upper electrodeand a degradation preventive layer at the boundary of ferroelectric layer/electrodes, or providing a step of decreasing a modified layer at the boundary of ferroelectric layer/upper electrode. This provides a thin ferroelectric film capacitor which is subjected to less fatigue and imprinting and which has less degradation of ferroelectric characteristic to attain a long life ferroelectric memory device.

Ferroelectric memory device including an upper protection electrode

Ferroelectric memory device

Along life ferroelectric memory device using a thin ferroelectric film capacitor as a memory capacitor is obtained by disposing a plurality of degradation preventive layers on an upper protection electrode and an upper electrode and a degradation preventive layer at the boundary of ferroelectric layer /electrodes or providing a step of decreasing a modified layer at the boundary of ferroelectric layer /upper electrode . This provides a thin ferroelectric film capacitor which is subjected to less fatigue and imprinting and which has less degradation of ferroelectric characteristic to attain a long life ferroelectric memory device.

Method of manufacturing a ferroelectric memory device

The present invention is a high quality semiconductor memory device using a ferroelectric thin film capacitor as a memory capacitor at a high manufacturing yield, the ferroelectric thin film of the capacitor is specified such that the relative standard deviation of a crystal grain sizes is 13% or less, to thereby ensure a high remanent polarization value and a small film fatigue (large rewritable number).

Semiconductor memory device having ferroelectric film and manufacturing method thereof

A shielding film having a higher lead content than that of a capacitive insulating film is formed under a lower electrode of a capacitor in a FeRAM memory cell, and another shielding film having a higher lead content than that of the capacitive insulating film is formed on an upper electrode. PZT films to be used as barrier layers are formed in the interlayer insulating films of the FeRAM memory cell. As a result, it is possible to prevent H or H O from entering an upper portion or a lower portion of the capacitor, and lead diffused from the capacitive insulating film can be compensated by lead included in the shielding films, and it is possible to prevent characteristics of the capacitive insulating film from being degraded.

In order to improve the dielectric constant, residual dielectric polarization, hysteresis characteristics, etc. of a high-dielectric or ferroelectric thin film for use in the formation of capacitive insulating films of capacitors of a DRAM or a ferroelectric RAM, a target having a density of at least 90% of the theoretical value is used in forming, by sputtering, a high-dielectric or ferroelectric thin film for use in the formation of capacitive insulating films of capacitors of a DRAM or a ferroelectric RAM.

Process for producing semiconductor integrated circuit device

Growing community of inventors

Tokyo, Japan

Keiichi Yoshizumi