The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 24, 2008
Filed:
Apr. 18, 2006
Kunihiko Kato, Tokyo, JP;
Masami Koketsu, Tokyo, JP;
Shigeya Toyokawa, Tokyo, JP;
Keiichi Yoshizumi, Tokyo, JP;
Hideki Yasuoka, Tokyo, JP;
Yasuhiro Takeda, Tokyo, JP;
Kunihiko Kato, Tokyo, JP;
Masami Koketsu, Tokyo, JP;
Shigeya Toyokawa, Tokyo, JP;
Keiichi Yoshizumi, Tokyo, JP;
Hideki Yasuoka, Tokyo, JP;
Yasuhiro Takeda, Tokyo, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device.