The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 20, 2010

Filed:

May. 06, 2008
Applicants:

Keiichi Yoshizumi, Tokyo, JP;

Kazuhisa Higuchi, Nanae, JP;

Takayuki Nakaji, Nanae, JP;

Masami Koketsu, Tokyo, JP;

Hideki Yasuoka, Hitachinaka, JP;

Inventors:

Keiichi Yoshizumi, Tokyo, JP;

Kazuhisa Higuchi, Nanae, JP;

Takayuki Nakaji, Nanae, JP;

Masami Koketsu, Tokyo, JP;

Hideki Yasuoka, Hitachinaka, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/8234 (2006.01); H01L 21/82 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.


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