Tokyo, Japan

Katsuo Yasuta

This inventor holds 7 USPTO granted patents and 3 published patent applications and 1 EPO patent. Top assignee: Kabushiki Kaisha Nihon Micronics. Active years: 2010-2022.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Katsuo Yasuta. Retrieved from https://idiyas.com/inventor/katsuo-yasuta

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 7 

% Patents Active = 85.7

 

Average Co-Inventor Count = 2.9

ph-index = 2

Forward Citations = 7(Granted Patents)


Location History:

  • Hirosaki, JP (2010)
  • Musashino, JP (2015)
  • Tokyo, JP (2012 - 2022)

Company Filing History:


Years Active: 2010-2022

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7 patents (USPTO):Explore Patents

Title: Katsuo Yasuta: Innovator in Semiconductor Inspection Technology

Introduction

Katsuo Yasuta is a prominent inventor based in Tokyo, Japan. He has made significant contributions to the field of semiconductor inspection technology, holding a total of 7 patents. His work focuses on enhancing the accuracy and efficiency of semiconductor device inspections.

Latest Patents

One of Yasuta's latest inventions is a prober designed to carry out accurate inspections of semiconductor devices in wafer state. This prober reduces the effects of external noises and current leakage while eliminating stray capacitance of the chuck stage against the prober housing. The design includes a chuck cover conductor with a bottom and side conductor, creating a space for the chuck stage. Additionally, an upper cover conductor allows for the passage of conducting support members for both front-side and back-side electrodes. This innovative design aims to improve the reliability of semiconductor inspections.

Another notable patent is a probe assembly for inspecting power semiconductor devices. This assembly features a probe block with multiple probe holding holes and probes that contact the semiconductor device under inspection. It also includes cooling units to suppress temperature rises during testing, ensuring accurate inspection results.

Career Highlights

Katsuo Yasuta is associated with Kabushiki Kaisha Nihon Micronics, a company known for its advancements in semiconductor technology. His work has been instrumental in developing tools that enhance the inspection process, contributing to the overall efficiency of semiconductor manufacturing.

Collaborations

Yasuta has collaborated with notable coworkers, including Kenichi Washio and Hikaru Masuta. Their combined expertise has fostered innovation in the semiconductor inspection field.

Conclusion

Katsuo Yasuta's contributions to semiconductor inspection technology through his patents and collaborations have significantly impacted the industry. His innovative designs continue to enhance the accuracy and efficiency of semiconductor device inspections.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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