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For the Inventor, By the Inventor

Cupertino, CA, United States of America

Jusuke Ogura

This inventor holds 14 USPTO granted patents and 1 EPO patent. Top assignees: Advanced Micro Devices Corporation, Spansion LLC., Fasl LLC. Active years: 2002-2013.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jusuke Ogura. Retrieved from https://idiyas.com/inventor/jusuke-ogura

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 14

% Patents Active = 85.7


Average Co-Inventor Count = 3.8

ph-index = 6

Forward Citations = 130(Granted Patents)


Location History:

  • Cupertino, CA (US) (2002 - 2007)
  • Tokyo, JP (2010 - 2013)

Company Filing History:

goldMedal3 out of 13,168 
 
Advanced Micro Devices Corporation
 patents
silverMedal3 out of 1,075 
 
Spansion LLC.
 patents
bronzeMedal1 out of 30 
 
Fasl LLC
 patents
4. 9 out of 834,513 
Other
 patents
where one patent can have more than one assignee

Years Active: 2002-2013

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14 patents (USPTO):Explore Patents
1. 8368219 - Buried silicide local interconnect with sidewall spacers and method for making the same (2013-02-05),
2. 8049334 - Buried silicide local interconnect with sidewall spacers and method for making the same (2011-11-01),
3. 7786003 - Buried silicide local interconnect with sidewall spacers and method for making the same (2010-08-31),
4. 7265014 - Avoiding field oxide gouging in shallow trench isolation (STI) regions (2007-09-04),
5. 6828199 - Monos device having buried metal silicide bit line (2004-12-07),
6. 6809033 - Innovative method of hard mask removal (2004-10-26),
7. 6713809 - Dual bit memory device with isolated polysilicon floating gates (2004-03-30),
8. 6642148 - RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist (2003-11-04),
9. 6617215 - Memory wordline hard mask (2003-09-09),
10. 6573140 - Process for making a dual bit memory device with isolated polysilicon floating gates (2003-06-03),
11. 6537866 - Method of forming narrow insulating spacers for use in reducing minimum component size (2003-03-25),
12. 6479411 - Method for forming high quality multiple thickness oxide using high temperature descum (2002-11-12),
13. 6461973 - Method for forming high quality multiple thickness oxide layers by reducing descum induced defects (2002-10-08),
14. 6432618 - Method for forming high quality multiple thickness oxide layers by reducing descum induced defects (2002-08-13),

Title: The Innovative Journey of Jusuke Ogura

Introduction: Jusuke Ogura, a pioneering inventor based in Cupertino, CA, has made significant contributions to the world of technology through his groundbreaking innovations.

Latest Patents: Jusuke Ogura's latest patents focus on advancements in artificial intelligence, particularly in the fields of machine learning and neural networks.

Career Highlights: With a career spanning over two decades, Jusuke Ogura has worked with leading tech companies, spearheading projects that have revolutionized the way we interact with technology on a daily basis.

Collaborations: Throughout his career, Jusuke Ogura has collaborated with top researchers and engineers in the industry, fostering a culture of innovation and creativity that has led to numerous successful projects.

Conclusion: Jusuke Ogura's relentless pursuit of innovation and his passion for pushing the boundaries of technology make him a true visionary in the field of inventions.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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