The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2011
Filed:
Jul. 26, 2010
Arvind Halliyal, Cupertino, CA (US);
Zoran Krivokapic, Santa Clara, CA (US);
Matthew S. Buynoski, Palo Alto, CA (US);
Nicholas H. Tripsas, San Jose, CA (US);
Minh Van Ngo, Freemont, CA (US);
Mark T. Ramsbey, Sunnyvale, CA (US);
Jeffrey A. Shields, Sunnyvale, CA (US);
Jusuke Ogura, Tokyo, JP;
Arvind Halliyal, Cupertino, CA (US);
Zoran Krivokapic, Santa Clara, CA (US);
Matthew S. Buynoski, Palo Alto, CA (US);
Nicholas H. Tripsas, San Jose, CA (US);
Minh Van Ngo, Freemont, CA (US);
Mark T. Ramsbey, Sunnyvale, CA (US);
Jeffrey A. Shields, Sunnyvale, CA (US);
Jusuke Ogura, Tokyo, JP;
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.