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For the Inventor, By the Inventor

Sacramento, CA, United States of America

Josh B Mastronarde

This inventor holds 49 USPTO granted patents and 11 published patent applications and 8 EPO patents, primarily in Graphics Processing. Top assignee: Intel Corporation. Active years: 2003-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Josh B Mastronarde. Retrieved from https://idiyas.com/inventor/josh-b-mastronarde

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 49 

% Patents Active = 93.9

 

Average Co-Inventor Count = 6.3

ph-index = 7

Forward Citations = 147(Granted Patents)


Location History:

  • Sacremento, CA (US) (2003)
  • Sacramento, CA (US) (2003 - 2024)

Company Filing History:

goldMedal49 out of 56,394 
 
Intel Corporation
 patents

Years Active: 2003-2026

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Areas of Expertise:
Graphics Virtualization
Compute Optimization
System-On-Chip
Power Management
Chiplet Configurations
Dynamic Voltage-Frequency
Frame Skipping
Facial Expression Rendering
Adaptive Compute Size
Deterministic Latency
Hybrid Processing Units
Contextual Configuration
49 patents (USPTO):Explore Patents
1. 12737001 - Timestamp correlated performance monitoring across a graphics processing unit (GPU) system (2026-09-15),
2. 12638971 - Bi-modal memory idle hysteresis for optimal add-in card accelerator performance and power (2026-05-26),
3. 12608871 - Apparatus and method for efficient graphics virtualization (2026-04-21),
4. 12205192 - Reduce power by frame skipping (2025-01-21),
5. 12198221 - Compute optimization mechanism for deep neural networks (2025-01-14),
6. 12141890 - Enabling product SKUs based on chiplet configurations (2024-11-12),
7. 12112398 - Disaggregation of system-on-chip (SOC) architecture (2024-10-08),
8. 12079155 - Graphics processor operation scheduling for deterministic latency (2024-09-03),
9. 12056789 - Disaggregation of system-on-chip (SOC) architecture (2024-08-06),
10. 11989076 - Dynamically power on/off processing clusters during execution (2024-05-21),
11. 11922535 - Compute optimization mechanism for deep neural networks (2024-03-05),
12. 11763416 - Disaggregation of system-on-chip (SOC) architecture (2023-09-19),
13. 11762696 - Hybrid low power homogenous grapics processing units (2023-09-19),
14. 11756150 - Disaggregation of system-on-chip (SOC) architecture (2023-09-12),
15. 11593910 - Compute optimization mechanism for deep neural networks (2023-02-28),

Title: The Inventive Journey of Josh B Mastronarde

Introduction: Josh B Mastronarde is a prolific inventor based in Sacramento, CA, known for his innovative contributions in various fields.

Latest Patents: Josh B Mastronarde holds several patents in the areas of technology, healthcare, and consumer products, showcasing his diverse range of interests and expertise.

Career Highlights: With a career spanning over two decades, Josh B Mastronarde has worked with leading companies to develop groundbreaking solutions that have made a significant impact in the industry.

Collaborations: Throughout his career, Josh B Mastronarde has collaborated with top researchers, engineers, and designers to bring his ideas to life, fostering a culture of innovation and creativity.

Conclusion: Josh B Mastronarde's passion for innovation and his relentless pursuit of excellence continue to inspire the next generation of inventors and entrepreneurs.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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