Intel Corporation

Josh B Mastronarde

Altug Koker

Balaji Vembu

Abhishek R Appu

Joydeep Ray

Travis T Schluessler

Linda L Hurd

Sanjeev S Jahagirdar

Nikos Kaburlasos

Wenyin Fu

Prasoonkumar Surti

Subramaniam M Maiyuran

Kamal Sinha

Ben J Ashbaugh

John H Feit

Varghese George

Narayan Srinivasa

Justin E Gottschlich

Karthik Vaidyanathan

Feng Chen

Adam T Lake

Eriko Nurvitadhi

Sara S Baghsorkhi

Nicolas C Galoppo Von Borries

Rajkishore Barik

Dukhwan Kim

Nadathur Rajagopalan Satish

Jeffery S Boles

Devan Burke

Tsung-Han Lin

Farshad Akhbari

Melaku Teshome

Lakshminarayanan Striramassarma

Iqbal Rajwani

Vikranth Vemulapalli

Naveen Matam

Lance Cheney

Eric Finley

Binoj Xavier

Elmoustapha Ould-Ahmed-Vall

Vasanth Ranganathan

Kiran Chand Veernapu

Ankur N Shah

Kai Xiao

Eric C Samson

Deepak Shashidhar Vembar

Guei-Yuan Lueh

David M Puffer

Atsuo Kuwahara

Thomas A Piazza

Abhishek Venkatesh

Pattabhiraman K

Bhushan M Borole

Aditya Sreenivas

Tomasz Janczak

Slawomir Grajewski

Eric J Asperheim

Niranjan L Cooray

Ravishankar Iyer

Scott R Janus

Selvakumar Panneer

Mike MacPherson

Jacek Kwiatkowski

Carson Brownlee

Nilesh K Jain

Sayan Lahiri

Jefferson Amstutz

Vivek Tiwari

Russell W Dyer

Saurabh Tangri

Jayakrishna P S

Himanshu Sinha

William S Dubel

Pradeep K Golconda

Shalini Sankar

In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive an input from one or more detectors proximate a display to present an output from a graphics pipeline, determine that a user is not interacting with the display, and in response to a determination that the user is not interacting with the display, to reduce a frame rendering rate of the graphics pipeline. Other embodiments are also disclosed and claimed.

Reduce power by frame skipping

Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Compute optimization mechanism for deep neural networks

A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, cache or DRAM memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

Enabling product SKUs based on chiplet configurations

Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

Disaggregation of system-on-chip (SOC) architecture

Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.

Graphics processor operation scheduling for deterministic latency

In an example, an apparatus comprises logic, at least partially comprising hardware logic, to power on a first set of processing clusters, dispatch a workload to the first set of processing clusters, detect a full operating state of the first set of processing clusters, and in response to the detection of a full operating state of the first set of processing clusters, to power on a second set of processing clusters. Other embodiments are also disclosed and claimed.

Dynamically power on/off processing clusters during execution

In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

Hybrid low power homogenous grapics processing units

An apparatus to facilitate compute optimization is disclosed. The apparatus includes one or more processing units to provide a first set of shader operations associated with a shader stage of a graphics pipeline, a scheduler to schedule shader threads for processing, and a field-programmable gate array (FPGA) dynamically configured to provide a second set of shader operations associated with the shader stage of the graphics pipeline.

An embodiment of a graphics apparatus may include a context engine to determine contextual information, a recommendation engine communicatively coupled to the context engine to determine a recommendation based on the contextual information, and a configuration engine communicatively coupled to the recommendation engine to adjust a configuration of a graphics operation based on the recommendation. Other embodiments are disclosed and claimed.

Contextual configuration adjuster for graphics

An apparatus and method are described for allocating local memories to virtual machines. For example, one embodiment of an apparatus comprises: a command streamer to queue commands from a plurality of virtual machines (VMs) or applications, the commands to be distributed from the command streamer and executed by graphics processing resources of a graphics processing unit (GPU); a tile cache to store graphics data associated with the plurality of VMs or applications as the commands are executed by the graphics processing resources; and tile cache allocation hardware logic to allocate a first portion of the tile cache to a first VM or application and a second portion of the tile cache to a second VM or application; the tile cache allocation hardware logic to further allocate a first region in system memory to store spill-over data when the first portion of the tile cache and/or the second portion of the file cache becomes full.

Apparatus and method for efficient graphics virtualization

Growing community of inventors

Sacramento, CA, United States of America

Josh B Mastronarde