IDiyas

For the Inventor, By the Inventor

Sunnyvale, CA, United States of America

John J Zasio

USPTO Granted Patents = 28

Average Co-Inventor Count = 1.9

ph-index = 14

Forward Citations = 720(Granted Patents)


Company Filing History:

goldMedal9 out of 39,230 
 
Fujitsu Corporation
 patents
silverMedal7 out of 19 
 
Storage Technology Partners
 patents
bronzeMedal4 out of 170 
 
Amdahl Corporation
 patents
4. 2 out of 720 
 
Teradyne, Inc.
 patents
5. 2 out of 8 
 
Alpine Microsystems, Inc.
 patents
6. 2 out of 37 
 
Hal Computer Systems, Inc.
 patents
7. 1 out of 1 
 
Aida Corporation
 patent
8. 1 out of 1 
 
Storage Technology Partners (through Stc Computer Research Corporation)
 patent

Years Active: 1976-2002

Loading Chart...
28 patents (USPTO):Explore Patents
1. 6337576 - Wafer-level burn-in (2002-01-08),
2. 6300161 - Module and method for interconnecting integrated circuits that facilitates high speed signal propagation with reduced noise (2001-10-09),
3. 5570036 - CMOS buffer circuit having power-down feature (1996-10-29),
4. 5541528 - CMOS buffer circuit having increased speed (1996-07-30),
5. 5095356 - Cellular integrated circuit and hierarchical method (1992-03-10),
6. 4969029 - Cellular integrated circuit and hierarchial method (1990-11-06),
7. 4937770 - Simulation system (1990-06-26),
8. 4924430 - Static timing analysis of semiconductor digital circuits (1990-05-08),
9. 4782283 - Apparatus for scan testing CMOS integrated systems (1988-11-01),
10. 4737933 - CMOS multiport general purpose register (1988-04-12),
11. 4587480 - Delay testing method for CMOS LSI and VLSI integrated circuits (1986-05-06),
12. 4553236 - System for detecting and correcting errors in a CMOS computer system (1985-11-12),
13. 4504783 - Test fixture for providing electrical access to each I/O pin of a VLSI (1985-03-12),
14. 4495629 - CMOS scannable latch (1985-01-22),
15. 4495628 - CMOS LSI and VLSI chips having internal delay testing capability (1985-01-22),

Title: Innovations and Contributions of John J Zasio

Introduction

John J Zasio, based in Sunnyvale, CA, is a prolific inventor known for his substantial contributions to the field of electronics and integrated circuits. With an impressive portfolio of 28 patents, Zasio has played a crucial role in developing methods and systems that enhance the performance and functionality of electronic devices.

Latest Patents

Among Zasio's latest patents are groundbreaking innovations such as the "Wafer-level burn-in" and a "Module and method for interconnecting integrated circuits." The Wafer-level burn-in patent outlines a method for testing circuits by using a flip-jumper that selectively connects signals to interconnect sites on the wafer, ensuring constant electrical communication. His integrated circuit interconnection module features an insulative body with conductive traces of varying resistivities, significantly facilitating high-speed signal propagation while reducing noise interference.

Career Highlights

Throughout his career, Zasio has made remarkable advances in the technology sector, particularly during his tenure at prominent companies like Fujitsu Corporation and Storage Technology Partners. His focus on innovation in circuit design and testing methods has brought about practical solutions that are widely implemented in the industry.

Collaborations

Zasio has collaborated with notable professionals in the field, including Fred K Buelow and Michael W Samuels. These collaborations have fostered an environment of innovation, allowing them to leverage each other's expertise to create cutting-edge technologies.

Conclusion

John J Zasio's contributions to the field of electronics, highlighted by his 28 patents, demonstrate his commitment to innovation and improvement in integrated circuits and electronic testing methods. His work continues to influence the industry, paving the way for future advancements in technology.

This text is generated by artificial intelligence and may not be accurate.
Please report any incorrect information to support@idiyas.com
Loading…