The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 26, 1990
Filed:
Dec. 29, 1988
Applicant:
Inventors:
Michael W Samuels, San Jose, CA (US);
John J Zasio, Sunnyvale, CA (US);
Assignee:
Teradyne, Inc., Boston, MA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06G / ; G11C / ;
U.S. Cl.
CPC ...
364578 ; 364900 ; 364490 ; 371 23 ; 36518905 ; 36523008 ;
Abstract
A levelized simulation system includes a means for storing a model of a logic system to be simulated. The logic system has a plurality of levels of logic which are synchronously clocked. A processing system including an arithmetic logic unit sequentially tests each element of said logic system, one level of logic at a time, thus each logic element in the first level is tested with the results there stored in a state memory, after which the logic elements of the second level of the logic system are tested and so on. During each test a comparison is made to determine whether there is a defect in the logic design.