Fujitsu Corporation

Storage Technology Partners

Amdahl Corporation

Teradyne, Inc.

Hal Computer Systems, Inc.

Alpine Microsystems, Inc.

Storage Technology Partners (through Stc Computer Research Corporation)

Aida Corporation

John J Zasio

Fred K Buelow

Michael W Samuels

Larry Cooke

Robert J Beall

Robert K Montoye

Martin P Goetz

Hisashige Ando

Hung C Lai

Laurence H Cooke

Creigton S Asato

Sammy K Brown

Andrew K Wiggin

George E Avery

Darrell R Parham

Raymond Paul

Ronald Tanizawa

Dwight Elvey

Michael Chiang

Kenneth C Choy

Tien-Lai Hwang

Allan Calamoneri

Tarang Patil

A method and a system for wafer level burn-in testing of a circuit featuring a flip-jumper to permit selectively connecting signals to the interconnect sites on the wafer that are in constant electrical communication with the circuit.

Wafer-level burn-in

A module and method for interconnecting integrated circuits. The module includes an insulative body that features conductive traces having differing resistivities associated therewith. To that end, the insulative body has, disposed therein, a conductive bond pad and a plurality of spaced apart conductive traces, one of which is in electrical communication with the bond pad, with each of the plurality of conductive traces are formed from a material having a resistivity associated therewith. The resistivity of the material from which one of the plurality of conductive traces is formed being greater than the resistivity of the material from which the remaining conductive traces are formed and defines a decoupling capacitor therebetween.

Module and method for interconnecting integrated circuits that facilitates high speed signal propagation with reduced noise

The gate of a P-channel pull-up transistor connected between an input node and a supply voltage in a buffer circuit is coupled to a test node. An N-channel pull-down transistor is connected between the input node and ground and has a gate connected to the test node. A logic low signal provided to the test node allows the circuit to operate normally. During test mode, a logic high signal is provided to the test node to turn off the P-channel pull-up transistor and thus prevent DC current flow in the circuit via the pull-up transistor. This logic high signal also turns on the pull-down transistor and, by shorting the input node to ground potential, prevents any other DC crossover currents from flowing in the circuit. Thus, during test mode, quiescent current flow resulting from small manufacturing defects in the circuit are obscured by larger DC currents and, as a result, may be readily measured to detect the presence of such small manufacturing defects.

CMOS buffer circuit having power-down feature

A buffer circuit which exhibits increased speed in transitions between binary states. A control transistor is coupled between a pull-up transistor and an input terminal. During low-to-high input signal transitions, the control transistor limits the signal swing at the input terminal such that small variations in the input terminal voltage result in larger voltage variations at the output terminal. During such transitions, the control transistor simultaneously decouples the input terminal from the pull-up transistor, thereby decoupling the input capacitance from the pull-up transistor. As a result, the speed with which the pull-up transistor can pull the output high is increased. As the number of input signal desired to be processed increases, the reduction in logic transition time becomes more significant. Some versions further include a pull-down transistor having a control terminal coupled to the gate of the pull-up transistor and to a power-down terminal. When an appropriate voltage is applied to the power-down terminal, the pull-up transistor is turned off and the pull-down transistor is turned on such that no DC current flows in the circuit.

CMOS buffer circuit having increased speed

Integrated circuit formed from a semiconductor body having a rectangular grid pattern formed on the body. The grid pattern is defined by lines extending at right angles to each other along X and Y axes. A plurality of basic cells are provided which have a plurality of active elements therein. Each of the basic cells is selected from a limited number of basic cells of different designs. Each of the basic cells is disposed within a rectangular area no greater than a predetermined size and overlying a plurality of grid lines on both the X and Y axes so that each basic cell overlies a plurality of intersections of the grid lines which define predetermined grid points. Each basic cell includes a power bus, a ground bus, input leads and an output having a predetermined arrangement with respect to certain grid points. The power bus and ground bus and the input leads and output of each basic cell are connected to the basic cell. Leads are provided for connecting the basic cells to form larger integrated circuit units which are called unit cells. The unit cells are connected to form still larger integrated circuits called a function block (FB).

Cellular integrated circuit and hierarchical method

Integrated circuit formed from a semiconductor body having a rectangular grid pattern formed on the body. The grid pattern is defined by lines extending at right angles to each other along X and Y axes. A plurality of basic cells are provided which have a plurality of active elements therein. Each of the basic cells is selected from a limited number of basic cells of different designs. Each of the basic cells is disposed within a rectangular area no greater than a predetermined size and overlying a plurality of grid lines on both the X and Y axes so that each basic cell overlies a plurlity of intersections of the grid lines which define predetermined grid points. Each basic cell includes a power bus, a ground bus, input leads and an output having a predetermined arrangement with respect to certain grid points. The power bus and ground bus and the input leads and output of each basic cell are connected to the basic cell. Leads are provided for connecting the basic cells to form larger integrated circuit units which are called unit cells. The unit cells are connected to form still larger integrated circuits called a function block (FB).

Cellular integrated circuit and hierarchial method

A levelized simulation system includes a means for storing a model of a logic system to be simulated. The logic system has a plurality of levels of logic which are synchronously clocked. A processing system including an arithmetic logic unit sequentially tests each element of said logic system, one level of logic at a time, thus each logic element in the first level is tested with the results there stored in a state memory, after which the logic elements of the second level of the logic system are tested and so on. During each test a comparison is made to determine whether there is a defect in the logic design.

Simulation system

The time verification scheme of the present invention operates without input stimulus to calculate delays along circuit paths including logic elements or cells from initial input to final output, or over sub-circuit paths, of a proposed logic design. The delay calculations include cell-dependent, and layout-dependent, and environmental-dependent factors to account for response delays on rising and falling signal; capacitance loading, temperature-dependency and voltage-dependency of a proposed logic design to provide output histograms and reports of information about overall performance, and timing violations of the proposed logic design with respect to operating parameters that can be selectively adjusted for manufacturing variations.

Static timing analysis of semiconductor digital circuits

Apparatus is disclosed for establishing scan-ring testing circuitry and control logic therefor on CMOS integrated circuit chips which can then be tested thereby during fabrication, after wire bonding and packaging, and while assembled and connected with other components on a printed circuit board. Tri-state buffers fabricated on the IC chip within the scan-ring control circuitry facilitate the operation of the scan-ring testing circuitry in several distinct operating modes which enable the functional circuitry of the integrated circuit to be electrically isolated from the associated signal pads for testing of the functional circuitry independently of circuitry connected to the signal pads, and for testing circuitry connected to the signal pads independently of the function circuitry of the chip.

Apparatus for scan testing CMOS integrated systems

A general purpose register including two input ports and two output ports, each port being addressed by an independent addressing circuit. The general purpose register includes a number of internal registers, and the provision of four independent addresses enables data to be written into two internal registers while data is being read out of two internal registers. The general purpose register also includes circuitry for transferring data from the input ports directly to the output ports without entering the data into the internal registers. Interchanging of bytes of data input words is also accomplished by the general purpose register. The internal registers, the four independent addressing circuits, the data transferring circuitry and additional undedicated circuitry are integrated into a single chip.

CMOS multiport general purpose register

A CMOS LSI or VLSI integrated circuit chip includes a shift register circuit that provides internal delay testing capability. The shift register circuit is disposed around the periphery of the chip and includes a large number of serially connected stages. One mode of operation allows a data signal to pass through the shift register circuit at a speed limited only by the propagation delays associated with the individual stages thereof. In this mode of operation, one net inversion is introduced into the data path and the output of a final stage of the shift register circuit is coupled to the input of a first stage of the shift register circuit, thereby creating a ring oscillator. The period of oscillation of this ring oscillator represents a measure of the average propagation delay times associated with the various circuit elements employed within the LSI or VLSI circuitry. Such delay measurements can readily be made at any level of packaging or system operation.

Delay testing method for CMOS LSI and VLSI integrated circuits

An improved scannable latch circuit allows its output to be monitored during effectively 100% of the system clock cycle. The circuit further provides dual isolated outputs, one of which is used as a latch output and the other of which is used as a shift-register output. A computer system, in which the scannable latch circuit is used, in conjunction with combinatorial logic and error detection circuitry, may thus monitor the latch output, which is not loaded down by the shift register output, for error detection and other purposes without having to slow down the system operating speed. A preferred embodiment of the scannable latch circuit includes first, second, and third latch elements. When operating a latch circuit, the first latch element operates as the 'master' and the second latch element operates as the 'slave' of a master/slave latch circuit. When operating as a shift register circuit, shift-in data is coupled to the second latch element, and this second latch element operates as the 'master' and the third latch element operates as the 'slave' of a master/slave latch through which data is selectively shifted by appropriate clock signals.

System for detecting and correcting errors in a CMOS computer system

A VLSI chip tester for defining and performing functional tests, delay tests, and DC parametric tests on VLSI chips. The VLSI chip under test is mounted to a paddle card which, in turn, is detachably held under pressure against a circuit board mounted in a test fixture. A connector is sandwiched between the paddle card and circuit board. The connector has insulated, spaced-apart conductors that are orthogonal to the paddle card and circuit board, and that provide electrical contact between each pin of the VLSI chip under test and a corresponding pad on the circuit board. Shift register circuits mounted to the circuit board provide a single stage corresponding to each I/O pin of the device under test. Each stage may function as an input or output device. A computer or computers are coupled to the shift register circuits through appropriate cabling and driver/receiver/termination circuits. Test data to be sent to or from the computer may be shifted serially into or out of the shift register circuits. Similarly, test data to be sent to or from the device under test may be shifted in parallel into or out of the shift register circuits. A self-test capability is provided.

Growing community of inventors

Sunnyvale, CA, United States of America

John J Zasio