IDiyas

For the Inventor, By the Inventor

Yokohama, Japan

Joerg W Wohlfahrt

USPTO Granted Patents = 14

Average Co-Inventor Count = 3.1

ph-index = 6

Forward Citations = 60(Granted Patents)


Location History:

  • Yokohama, JP (2004 - 2005)
  • Kanagawa-ken, JP (2004 - 2006)
  • Kanagawa, JP (2003 - 2007)

Company Filing History:

goldMedal12 out of 14,705 
 
Infineon Technologies Ag
 patents
silverMedal1 out of 48 
 
Infineon Technologies Richmond, LP
 patents
bronzeMedal1 out of 52,711 
 
Kabushiki Kaisha Toshiba
 patents
4. 1 out of 832,680 
Other
 patents
where one patent can have more than one assignee

Years Active: 2003-2007

where 'Filed Patents' based on already Granted Patents

14 patents (USPTO):
1. 7187602 - Reducing memory failures in integrated circuits (2007-03-06),
2. 6999887 - Memory cell signal window testing apparatus (2006-02-14),
3. 6903959 - Sensing of memory integrated circuits (2005-06-07),
4. 6885597 - Sensing test circuit (2005-04-26),
5. 6856560 - Redundancy in series grouped memory architecture (2005-02-15),
6. 6826099 - 2T2C signal margin test mode using a defined charge and discharge of BL and /BL (2004-11-30),
7. 6807084 - FeRAM memory device (2004-10-19),
8. 6800890 - Memory architecture with series grouped by cells (2004-10-05),
9. 6731554 - 2T2C signal margin test mode using resistive element (2004-05-04),
10. 6731529 - Variable capacitances for memory cells within a cell group (2004-05-04),
11. 6720598 - Series memory architecture (2004-04-13),
12. 6717431 - Method for semiconductor yield loss calculation (2004-04-06),
13. 6707699 - Historical information storage for integrated circuits (2004-03-16),
14. 6639824 - Memory architecture (2003-10-28),
This text is generated by artificial intelligence and may not be accurate.
Please report any incorrect information to support@idiyas.com
Loading…